Datasheet 5P35021 (IDT) - 4
| 制造商 | IDT |
| 描述 | Programmable VersaClock Clock Generator |
| 页数 / 页 | 46 / 4 — Pin Descriptions Table 1. Pin Descriptions. Number. Name. Type. … |
| 修订版 | 20191004 |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
Pin Descriptions Table 1. Pin Descriptions. Number. Name. Type. Description
该数据表的模型线
文件文字版本
link to page 9 5P35021 Datasheet
Pin Descriptions Table 1. Pin Descriptions Number Name Type Description
1 VDDA Power VDD 3.3V. 2 SDA_DFC0 I/O I2C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status. I2C CLK pin. SEL_DFC/ SEL_DFC is a latch input pin during the power-up. 3 Input SCL_DFC1 High on power-on: I2C mode as SCLK function. Low on power-on: SCL and SDA as DFC function control pins. 4 CLKIN/X2 I/O Crystal oscillator interface output or differential clock input pin (CLKIN). 5 CLKINB/X1 Input Crystal oscillator interface input or differential clock input pin (CLKINB). 6 VBAT Power Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 2.5V–3.3V. 7 VSS Power Connect to ground 8 VDD33 Power VDD 3.3V. 9 VSSSE1 Power Connect to ground 10 VDDSE1 Power Output power supply. Connect to 1.8V–3.3V. Sets output voltage levels for SE1. 11 SE1 Output Output clock SE1. OE1’s function selected from OTP pre-programmed register bits. 12 OE1 Input OE1 pull to 6.5V when burn OTP registers. Refer to OE Pin Functions table for details. 13 VDDDIFF1 Power Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF1. Differential clock output 1_Complement; can be OTP pre-programmed to 14 DIFF1B Output LVCMOS/LPHCSL/LVDS/LVPECL output type. Differential clock output 1_True; can be OTP pre-programmed to 15 DIFF1 Output LVCMOS/LP-HCSL/LVDS/LVPECL output type. 16 VSSDIFF1 Power Connect to ground 17 VDDDIFF2 Power Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF2. Differential clock output 2_Complement; can be OTP pre-programmed to 18 DIFF2B Output LVCMOS/LPHCSL/LVDS/LVPECL output type. Differential clock output 2_True; can be OTP pre-programmed to 19 DIFF2 Output LVCMOS/LP-HCSL/LVDS/LVPECL output type. 20 VSSDIFF2 Power Connect to ground. EPAD Power Connect to ground pad. ©2019 Integrated Device Technology, Inc. 4 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History
Pin Descriptions Table 1. Pin Descriptions Number Name Type Description
1 VDDA Power VDD 3.3V. 2 SDA_DFC0 I/O I2C data pin. The pin can be DFC0 function by pin 3 SEL_DFC power-on latch status. I2C CLK pin. SEL_DFC/ SEL_DFC is a latch input pin during the power-up. 3 Input SCL_DFC1 High on power-on: I2C mode as SCLK function. Low on power-on: SCL and SDA as DFC function control pins. 4 CLKIN/X2 I/O Crystal oscillator interface output or differential clock input pin (CLKIN). 5 CLKINB/X1 Input Crystal oscillator interface input or differential clock input pin (CLKINB). 6 VBAT Power Power supply pin for 32.768kHz DCO; usually connect to coin cell battery, 2.5V–3.3V. 7 VSS Power Connect to ground 8 VDD33 Power VDD 3.3V. 9 VSSSE1 Power Connect to ground 10 VDDSE1 Power Output power supply. Connect to 1.8V–3.3V. Sets output voltage levels for SE1. 11 SE1 Output Output clock SE1. OE1’s function selected from OTP pre-programmed register bits. 12 OE1 Input OE1 pull to 6.5V when burn OTP registers. Refer to OE Pin Functions table for details. 13 VDDDIFF1 Power Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF1. Differential clock output 1_Complement; can be OTP pre-programmed to 14 DIFF1B Output LVCMOS/LPHCSL/LVDS/LVPECL output type. Differential clock output 1_True; can be OTP pre-programmed to 15 DIFF1 Output LVCMOS/LP-HCSL/LVDS/LVPECL output type. 16 VSSDIFF1 Power Connect to ground 17 VDDDIFF2 Power Output power supply. Connect to 2.5V–3.3V. Sets output voltage levels for DIFF2. Differential clock output 2_Complement; can be OTP pre-programmed to 18 DIFF2B Output LVCMOS/LPHCSL/LVDS/LVPECL output type. Differential clock output 2_True; can be OTP pre-programmed to 19 DIFF2 Output LVCMOS/LP-HCSL/LVDS/LVPECL output type. 20 VSSDIFF2 Power Connect to ground. EPAD Power Connect to ground pad. ©2019 Integrated Device Technology, Inc. 4 October 4, 2019 Document Outline Description Typical Applications Key Specifications Features Output Features Block Diagram Pin Assignments Figure 1. Pin Assignments for 3 x 3 mm 20-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Sources Table 3. Output Source Table 4. Output Source Selection Register Settings Table 5. DIFF1 Output Table 6. DIFF2 Output Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Timer Function Description Figure 5. Timer Functions OE Pin Function Table 8. OE Pin Functions Table 9. OE Pin Function Summary Table 10. PD# Priority Reference Input and Selection Crystal Input (X1/X2) Table 11. Programmable Tuning Caps Spread Spectrum Analog Spread Spectrum Digital Spread Spectrum Figure 6. Digital Spread Spectrum VBAT Table 12. VBAT Switching Threshold ORT–VCO Overshoot Reduction Technology PLL Features and Descriptions Table 13. Output 1 Divider Table 14. Output 2, 4, and 5 Divider Table 15. Output 3 Divider Output Clock Test Conditions Figure 7. LVCMOS Output Test Conditions Figure 8. LP-HCSL Output Test Conditions Absolute Maximum Ratings Table 16. Absolute Maximum Ratings Recommended Operating Conditions Table 17. Recommended Operating Conditions Electrical Characteristics Table 18. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Table 19. Crystal Characteristics Table 20. DC Electrical Characteristics (Industrial)1,2 Table 21. DC Electrical Characteristics (Automotive)1,2 Table 22. Input Parameters1,2 Table 23. Power Consumption of 32.768kHz Output Only Operation Table 24. DC Electrical Characteristics – 3.3V LVCMOS Table 25. DC Electrical Characteristics – 2.5V LVCMOS Table 26. DC Electrical Characteristics – 1.8V LVCMOS Table 27. Electrical Characteristics – DIF 0.7V LPHCSL Differential Outputs Table 28. Electrical Characteristics – LVDS Table 29. Electrical Characteristics – LVPECL Figure 9. Output Differential Voltage Swing AC Electrical Characteristics Table 30. AC Electrical Characteristics PCI Express Jitter Specifications Table 31. PCI Express Jitter Specifications Spread Spectrum Generation Specifications Table 32. Spread Spectrum Generation Specifications I2C Bus Characteristics Table 33. I2C Bus DC Characteristics Table 34. I2C Bus AC Characteristics I2C Mode Operations Figure 10. I2C Slave Read and Write Cycle Sequencing Glossary of Features Table 35. Glossary of Features Package Outline Drawings Marking Diagrams (industrial) Marking Diagrams (automotive) Ordering Information Revision History