Datasheet ADN8810 (Analog Devices) - 14

ADN8810 Data Sheet OUTLINE DIMENSIONS DETAIL A 4.10 (JEDEC 95) 0.30 4.00 SQ 0.25 PIN 1 3.90 0.20 INDICATOR 19 24 PIN 1 INDIC ATOR AREA OPTIONS 18 1 (SEE DETAIL A) 0.50 BSC 2.20 EXPOSED PAD 2.10 SQ 2.00 13 6 0.50 12 7 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 SIDE VIEW 0.05 MAX THE PIN CONFIGURATION AND 0.70 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.203 REF A 2017- -004714 21- G PK COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8. 02-
Figure 26. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option
ADN8810ACPZ –40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-10 ADN8810ACPZ-REEL7 –40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-10 1 Z = RoHS Compliant Part.
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Rev. C | Page 14 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY FUNCTIONAL DESCRIPTION SETTING FULL-SCALE OUTPUT CURRENT POWER SUPPLIES SERIAL DATA INTERFACE STANDBY AND RESET MODES POWER DISSIPATION USING MULTIPLE ADN8810 DEVICES FOR ADDITIONAL OUTPUT CURRENT ADDING DITHER TO THE OUTPUT CURRENT DRIVING COMMON-ANODE LASER DIODES PCB LAYOUT RECOMMENDATIONS SUGGESTED PAD LAYOUT FOR CP-24 PACKAGE OUTLINE DIMENSIONS ORDERING GUIDE