Datasheet 8V97003 (IDT) - 64

48-VFQFPN, Package Outline Drawing
7.0 x7.0 x 0.85 mm Body, 0.5mm Pitch, Epad 5.30 x 5.30 mm NLG48P3, PSC-4203-04, Rev 02, Page 1 © Integrated Device Technology, Inc. Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History