Preliminary Datasheet EZ-PD CCG6DF, CCG6SF (Cypress) - 46

PRELIMINARY EZ-PD CCG6DF, CCG6SF Acronyms Table 43. Acronyms Used in this Document
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Table 43. Acronyms Used in this Document Acronym Description Acronym Description
ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO ADC analog-to-digital converter I/O input/output, see also GPIO API application programming interface IPOR imprecise POR Arm® advanced RISC machine, a CPU architecture IRQ interrupt request CC configuration channel ISR interrupt service request CSN current sense negative LVD low-voltage detect BCC battery charger controller LVTTL low-voltage transistor-transistor logic BOD Brown out Detect MCU microcontroller unit CC configuration channel MDI medium density CPU central processing unit NC no connect CRC cyclic redundancy check, an error-checking protocol NGDO N-FET gate driver output CS current sense NMI nonmaskable interrupt CSA current sense amplifier NVIC nested vectored interrupt controller CSN current sense negative opamp operational amplifier CSP current sense positive OCP overcurrent protection DFP downstream facing port OVP overvoltage protection DM data minus PCB printed circuit board DP data plus signal PD power delivery DP DisplayPort, digital display interface developed by PGA programmable gain amplifier Video Electronics Standards Association PHY physical layer DIO digital input/output, GPIO with only digital POR power-on reset capabilities, no analog. See GPIO. PRES precise power-on reset DRP dual role power PSoC® Programmable System-on-Chip™ EC embedded controller PWM pulse-width modulator EEPROM electrically erasable programmable read-only memory RAM random-access memory EMCA a USB cable that includes an IC that reports cable RCP reverse current protection characteristics (e.g., current rating) to the Type-C RISC reduced-instruction-set computing ports RMS root-mean-square EMI electromagnetic interference RTC real-time clock ESD electrostatic discharge RX receive FPB flash patch and breakpoint SAR successive approximation register FRS fast role swap SCB serial communication block FS full-speed SCL I2C serial clock GPIO general-purpose input/output HDI high density interconnect SDA I2C serial data HSCSA high-side current sense amplifier S/H sample and hold IC integrated circuit SPI Serial Peripheral Interface, a communications protocol IDE integrated development environment SRAM static random access memory I2C, or IIC Inter-Integrated Circuit, a communications SWD serial wire debug, a test protocol protocol Document Number: 002-27161 Rev. *E Page 46 of 50 Document Outline EZ-PD CCG6DF, CCG6SF, USB Type-C Port Controller General Description Applications Features USB-PD Type-C Mux Integrated Provider VBUS Load Switch LDO 32-bit MCU Subsystem Integrated Digital Blocks Authentication Clocks and Oscillators Operating Range Hot-Swappable I/Os Packages Logic Block Diagram CCG6DF/CCG6SF Functional Diagram Contents Functional Overview MCU Subsystem CPU Flash, SROM, and RAM USB-PD Subsystem (SS) USB-PD Physical Layer VCONN FET ADC SBU Pass-Through Switch and USB HS Mux Provider Load Switch Undervoltage and Overvoltage Protection on VBUS High-side Current Sense Amplifier for VBUS VBUS Reverse Current Protection VBUS Short Circuit Protection VBUS Discharge VBUS Regulator Gate Driver for VBUS NFET VBUS Tolerant SBU and CC Lines Serial Communication Block (SCB) Timer, Counter, Pulse-Width Modulator (TCPWM) True Random Number Generator (TRNG) GPIO Interface System Resources Watchdog Timer (WDT) Clock System IMO Clock Source ILO Clock Source Power Pinouts Application Diagrams CCG6DF, CCG6SF Layout Design Guidelines for BGA Package Usage of Via Size of 8-mil drill/16-mil diameter and 10-mil drill/16-mil diameter Layer Stack-up Top Layer Fan Out Via Count for GND Pads Via Count for Provider Pads High-Speed (DP_SYS, DM_SYS) USB Connections CC Connections CC lines for CCG6DF/CCG6SF devices carry ~500-mA current. In the top layer, two CC pads are shorted using 0.2mm trace width and connected to other layers through one via. The capacitors are placed on bottom layer and are routed to the Type-C Connecto... Rsense and Capacitor Connections for Provider VBUS The differential signal from Rsense should be length matched. The capacitor for Provider VBUS should be as close as possible to the Rsense and connected using copper shape. Figure 19 and Figure 20 show routing for Rsense. Trace Width Details for Critical Signals VDDIO, VCCD, VSYS, and VDDD Connections Figure 21 and Figure 22 show how the VDDIO, VDDD, VSYS, and VCCD signals get routed amongst the top and bottom layers. Capacitor Connections for CC Lines and Bypass Capacitors for VDDIO, VDDD, VCCD, and VSYS Pins Figure 23 shows how the relevant capacitors can be placed for via sizes of 8-mil drill, 16-mil diameter or 10-mil drill, 16-mil diameter. Electrical Specifications Absolute Maximum Ratings Device-Level Specifications DC Specifications CPU GPIO XRES Digital Peripherals Pulse Width Modulation (PWM) for GPIO Pins I2C UART SPI Memory System Resources Power-on-Reset (POR) with Brown Out SWD Interface Internal Main Oscillator Internal Low-speed Oscillator PD Analog-to-Digital Converter VSYS Switch CSA VBUS UV/OV Provider Side RCP SBU Switch DP/DM Switch VCONN Switch VBUS Ordering Information Ordering Code Definitions Packaging Acronyms Document Conventions Units of Measure References and Links to Applications Collateral Knowledge Base Articles Application Notes Reference Designs Kits Datasheets Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support