link to page 5 Forced Frequency Resonant Flyback controllerRepresentative Block Diagram 2Representative Block Diagram Figure 3 shows a simplified top level block diagram of the IC functionality.
HV XDPS21071HV Startup-cellBang-Bang Ctrl Closed/Open Startup-Cell VVCCBBoff = 20.5 V Driver VVCCBBonAR/LM = 9 V Vbulk Brown-outProtection QM IHVBO = 0.443 mA D1 VbulkVbulk Brown-inmeasurementProtectionOvertemperature R I M HVBI = 1.15 mA Detection TJOTP = 130 °C VCC Brown-in & VCC Protection VVCCBI = 9.1 V ProtectionHW ResetUVLOModes VVCCon = 20.5 V Auto RestartPowerMode VVCCoffx = 7.2 V / 9.6 V ManagementVout OVLatchVout reflected VoltageProtection ZCD Mode 1 k Measurement VZCDOVP = 2.75 V Soft-StartOpen Loop Timer tMFIOH = 31.3 ms Frequency clampGate DriverFFR ModePWMFrequency Law fSW GD0 With ZVS PulseLogicGeneration C2 VCSPK V V MFIO MFIOH = 2.41 V PDC VVDDP = 3.3 V VMFIO Gate Driver RMFIOPU GD1 Burst Mode FunctionVcs_offset MFIO C3 VMFIOBMEX1 BM Exit C5 VMFIOBMWK on-phase BM 2-pointBM CtrlRegulation C6 off-phase VMFIOBMPA C7 V BM Entry MFIOBMEN Cycle by Cycle Peak Current Ctrl OCP1 CS tCSLEB V 1 k 10k CSPK 1 pF Auto Restart2nd Level Overcurrent DetectionInput Detection OCP2 tCSOCP2BL VCSOCP2 = 0.8 V VVDDP = 3.3 V IGPIOLPU UARTParameter GPIO CommunicationConfigurationFigure 3Representative Block Diagram of XDPS21071 Data Sheet 5 Revision 2.0 2019-10-30