Product Brief PIC16(L)F1885X/7X (Microchip) - 6
| 制造商 | Microchip |
| 描述 | Full-Featured 28/40-Pin Microcontroller |
| 页数 / 页 | 16 / 6 — PIC16(L)F1885X/7X 29 RA6. 28 RA7. 27 VSS F1. L) 3. 4 88 5 /. 75 26 VDD. … |
| 文件格式/大小 | PDF / 184 Kb |
| 文件语言 | 英语 |
PIC16(L)F1885X/7X 29 RA6. 28 RA7. 27 VSS F1. L) 3. 4 88 5 /. 75 26 VDD. 25 RE2 8. 18 6 88. 76 7. 8 24 RE1
该数据表的模型线
- PIC16F18857-E/ML PIC16F18857-E/MLVAO PIC16F18857-E/SO PIC16F18857-E/SP PIC16F18857-E/SS PIC16F18857-E/SSVAO PIC16F18857-I/ML PIC16F18857-I/SO PIC16F18857-I/SP PIC16F18857-I/SS PIC16F18857-I/SSVAO PIC16F18857T-E/MLVAO PIC16F18857T-E/SS PIC16F18857T-E/SSVAO PIC16F18857T-I/ML PIC16F18857T-I/SO PIC16F18857T-I/SS PIC16F18857T-I/SSC02 PIC16F18857T-I/SSVAO PIC16LF18857-E/ML PIC16LF18857-E/SO PIC16LF18857-E/SP PIC16LF18857-E/SS PIC16LF18857-I/ML PIC16LF18857-I/SO PIC16LF18857-I/SP PIC16LF18857-I/SS PIC16LF18857T-I/ML PIC16LF18857T-I/SO PIC16LF18857T-I/SS
- PIC16F18877-E/ML PIC16F18877-E/MV PIC16F18877-E/MVVAO PIC16F18877-E/P PIC16F18877-E/PT PIC16F18877-I/ML PIC16F18877-I/MV PIC16F18877-I/P PIC16F18877-I/PREL PIC16F18877-I/PT PIC16F18877T-E/MV PIC16F18877T-E/MVVAO PIC16F18877T-I/ML PIC16F18877T-I/MV PIC16F18877T-I/PT PIC16LF18877-E/ML PIC16LF18877-E/MV PIC16LF18877-E/P PIC16LF18877-E/PT PIC16LF18877-I/ML PIC16LF18877-I/MV PIC16LF18877-I/MVC04 PIC16LF18877-I/P PIC16LF18877-I/PT PIC16LF18877T-I/MV PIC16LF18877T-I/MVC04 PIC16LF18877T-I/PT PIC16LF18877T-I/PTC01 PIC16LF18877T-I/PTRA3
文件文字版本
PIC16(L)F1885X/7X 29 RA6
28 RA7
27 VSS F1
L) 3
4 88 5 /
75 26 VDD
25 RE2 8
18 6 88
/1
76 7
8 24 RE1
23 RE0 20 18 17 16 15 14 13 22 RA5
21 RA4 RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3 11 10 19 77 9 12 31 32 34 33 35 36 37 39 38 30 RC0 (
16 RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2 C
PI RC7 1
RD4 2 40 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1 Pin Diagram – 40-Pin UQFN (5x5) Note 1:
2:
3: See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level. 1
2
3
4
5
6
7
8
9
10
11 C1
PI
8
F1
L)
6(
87
18
5/
87
18
6/
87 33
32
31
30
29
28
27
26
25
24
23 RA6
RA7
VSS
VSS
VDD
VDD
RE2
RE1
RE0
RA5
RA4 RB3
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3 12
13
14
15
16
17
18
19
20
21
22 7 RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
RB0
RB1
RB2 44
43
42
41
40
39
38
37
36
35
34 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0 Pin Diagram – 44-Pin QFN (8x8) Note 1:
2:
3: See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level. DS40001768A-page 6 Advance Information 2014 Microchip Technology Inc.
28 RA7
27 VSS F1
L) 3
4 88 5 /
75 26 VDD
25 RE2 8
18 6 88
/1
76 7
8 24 RE1
23 RE0 20 18 17 16 15 14 13 22 RA5
21 RA4 RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3 11 10 19 77 9 12 31 32 34 33 35 36 37 39 38 30 RC0 (
16 RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2 C
PI RC7 1
RD4 2 40 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1 Pin Diagram – 40-Pin UQFN (5x5) Note 1:
2:
3: See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level. 1
2
3
4
5
6
7
8
9
10
11 C1
PI
8
F1
L)
6(
87
18
5/
87
18
6/
87 33
32
31
30
29
28
27
26
25
24
23 RA6
RA7
VSS
VSS
VDD
VDD
RE2
RE1
RE0
RA5
RA4 RB3
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3 12
13
14
15
16
17
18
19
20
21
22 7 RC7
RD4
RD5
RD6
RD7
VSS
VDD
VDD
RB0
RB1
RB2 44
43
42
41
40
39
38
37
36
35
34 RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0 Pin Diagram – 44-Pin QFN (8x8) Note 1:
2:
3: See Table 4 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float
may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level. DS40001768A-page 6 Advance Information 2014 Microchip Technology Inc.