Datasheet ADP5071 (Analog Devices) - 24
| 制造商 | Analog Devices |
| 描述 | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| 页数 / 页 | 27 / 24 — ADP5071. Data Sheet. SUPER LOW NOISE WITH OPTIONAL LDOS. RC1. INBK. … |
| 修订版 | E |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
ADP5071. Data Sheet. SUPER LOW NOISE WITH OPTIONAL LDOS. RC1. INBK. 5.6kΩ. 3.3µH. COMP1. ADP7142. DFLS240. VPOS = +15V. +16V. SW1. 47nF. VIN. VOUT. EN1
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ADP5071 Data Sheet SUPER LOW NOISE WITH OPTIONAL LDOS
Low dropout regulators (LDOs) can be added to the ADP5071 Table 12 shows recommended companion devices, and Figure 48 output to provide super low noise supplies for high performance shows a typical application schematic for ±15 V generation ADCs, digital-to-analog converters (DACs), and other precision from a +5 V supply. applications.
ADP5071 RC1 SS INBK L1 5.6kΩ 3.3µH COMP1 D1 ADP7142 C DFLS240 VPOS = +15V C1 +16V SW1 47nF VIN VOUT EN1 C R C R IN3 FT3 NR3 FT1 1µF 20kΩ 2.15MΩ ADJ 1µF COUT3 2.2µF (5V) VREG FB1 COUT1 RFB3 RNR3 C R 10µF 10kΩ 1kΩ VREG FB1 1µF PVIN1 113kΩ EN SS VIN GND PVIN2 +5V C PGND C IN1 SS3 PVINSYS 10µF 1nF CVREF 1µF ADP7182 EN2 VREF VNEG = –15V R C EN VOUT R FB2 OUT2 C2 RFT4 CNR4 12kΩ 100kΩ 10µF 52.3kΩ 0.1µF COUT4 COMP2 FB2 2.2µF R ADJ C FT2 RFB4 R C2 NR4 SYNC/FREQ 2.1MΩ 4.64kΩ 47nF –16V 4.64kΩ SLEW SW2 VIN CIN4 GND SEQ D2 AGND 2.2µF DFLS240 L2
047
6.8µH
12069- Figure 48. Super Low Noise ±15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO)
Table 12. Recommended LDOs for Super Low Noise Operation Parameter ADP7102 ADP7104 ADP7105 ADP7118 ADP7142 ADP7182
VIN Range 3.3 V to 20 V 3.3 V to 20 V 3.3 V to 20 V 2.7 V to 20 V 2.7 V to 40 V −2.7 V to −28 V Fixed VOUT 1.5 V to 9 V 1.5 V to 9 V 1.8 V, 3.3 V, 5 V 1.2 V to 5 V 1.2 V to 5 V −1.8 V to −5 V Adjustable VOUT 1.22 V to 19 V 1.22 V to 19 V 1.22 V to 19 V 1.2 V to 19 V 1.2 V to 39 V −1.22 V to−27 V IOUT 300 mA 500 mA 500 mA 200 mA 200 mA −200 mA IQ at No Load 400 µA 400 µA 400 µA 50 µA 50 µA −33 µA ISHDN Typical 40 µA 40 µA 40 µA 2 µA 2 µA −2 µA Soft Start No No Yes Yes Yes No PGOOD Yes Yes Yes No No No Noise (Fixed), 10 Hz 15 µV rms 15 µV rms 15 µV rms 11 µV rms 11 µV rms 18 µV rms to 100 kHz PSRR (100 kHz) 60 dB 60 dB 60 dB 68 dB 68 dB 45 dB PSRR (1 MHz) 40 dB 40 dB 40 dB 50 dB 50 dB 45 dB Package 8-lead LFCSP, 8-lead LFCSP, 8-lead LFCSP, 6-lead LFCSP, 6-lead LFCSP, 6-lead LFCSP, 8-lead 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead SOIC, 8-lead SOIC, LFCSP, 5-lead TSOT 5-lead TSOT 5-lead TSOT Rev. E | Page 24 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
ADP5071 Data Sheet SUPER LOW NOISE WITH OPTIONAL LDOS
Low dropout regulators (LDOs) can be added to the ADP5071 Table 12 shows recommended companion devices, and Figure 48 output to provide super low noise supplies for high performance shows a typical application schematic for ±15 V generation ADCs, digital-to-analog converters (DACs), and other precision from a +5 V supply. applications.
ADP5071 RC1 SS INBK L1 5.6kΩ 3.3µH COMP1 D1 ADP7142 C DFLS240 VPOS = +15V C1 +16V SW1 47nF VIN VOUT EN1 C R C R IN3 FT3 NR3 FT1 1µF 20kΩ 2.15MΩ ADJ 1µF COUT3 2.2µF (5V) VREG FB1 COUT1 RFB3 RNR3 C R 10µF 10kΩ 1kΩ VREG FB1 1µF PVIN1 113kΩ EN SS VIN GND PVIN2 +5V C PGND C IN1 SS3 PVINSYS 10µF 1nF CVREF 1µF ADP7182 EN2 VREF VNEG = –15V R C EN VOUT R FB2 OUT2 C2 RFT4 CNR4 12kΩ 100kΩ 10µF 52.3kΩ 0.1µF COUT4 COMP2 FB2 2.2µF R ADJ C FT2 RFB4 R C2 NR4 SYNC/FREQ 2.1MΩ 4.64kΩ 47nF –16V 4.64kΩ SLEW SW2 VIN CIN4 GND SEQ D2 AGND 2.2µF DFLS240 L2
047
6.8µH
12069- Figure 48. Super Low Noise ±15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO)
Table 12. Recommended LDOs for Super Low Noise Operation Parameter ADP7102 ADP7104 ADP7105 ADP7118 ADP7142 ADP7182
VIN Range 3.3 V to 20 V 3.3 V to 20 V 3.3 V to 20 V 2.7 V to 20 V 2.7 V to 40 V −2.7 V to −28 V Fixed VOUT 1.5 V to 9 V 1.5 V to 9 V 1.8 V, 3.3 V, 5 V 1.2 V to 5 V 1.2 V to 5 V −1.8 V to −5 V Adjustable VOUT 1.22 V to 19 V 1.22 V to 19 V 1.22 V to 19 V 1.2 V to 19 V 1.2 V to 39 V −1.22 V to−27 V IOUT 300 mA 500 mA 500 mA 200 mA 200 mA −200 mA IQ at No Load 400 µA 400 µA 400 µA 50 µA 50 µA −33 µA ISHDN Typical 40 µA 40 µA 40 µA 2 µA 2 µA −2 µA Soft Start No No Yes Yes Yes No PGOOD Yes Yes Yes No No No Noise (Fixed), 10 Hz 15 µV rms 15 µV rms 15 µV rms 11 µV rms 11 µV rms 18 µV rms to 100 kHz PSRR (100 kHz) 60 dB 60 dB 60 dB 68 dB 68 dB 45 dB PSRR (1 MHz) 40 dB 40 dB 40 dB 50 dB 50 dB 45 dB Package 8-lead LFCSP, 8-lead LFCSP, 8-lead LFCSP, 6-lead LFCSP, 6-lead LFCSP, 6-lead LFCSP, 8-lead 8-lead SOIC 8-lead SOIC 8-lead SOIC 8-lead SOIC, 8-lead SOIC, LFCSP, 5-lead TSOT 5-lead TSOT 5-lead TSOT Rev. E | Page 24 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide