Datasheet ADP5071 (Analog Devices) - 20

link to page 23
ADP5071 Data Sheet
When the ADP5071 inverting regulator is operated in CCM at GCS1 is the current sense transconductance gain (the inductor duty cycles greater than 50%, slope compensation is required to current divided by the voltage at COMP1), which is internal y stabilize the current mode loop. For stable current mode operation, set by the ADP5071and is 12.5 A/V. ensure that the selected inductance is equal to or greater than ZOUT1 is the impedance of the load in paral el with the output the minimum calculated inductance, LMIN2, for the application capacitor. parameters in the fol owing equation: To determine the crossover frequency (fC1), it is important to   note that, at that frequency, the compensation impedance (ZCOMP1) L2 > L = V ×  0.13 −  (µH) MIN2 IN  0.16 is dominated by a resistor (RC1), and the output impedance (ZOUT1)  1 ( − DUT 2 Y )  is dominated by the impedance of an output capacitor (COUT1). Table 11 suggests a series of inductors to use with the ADP5071 Therefore, when solving for the crossover frequency, the equation inverting regulator. (by definition of the crossover frequency) is simplified to
LOOP COMPENSATION
A = V V FB1 × IN × G × R × G × VL1 M1 C1 CS1 The ADP5071 uses external components to compensate the V V POS POS regulator loop, allowing the optimization of the loop dynamics 1 = 1 for a given application. It is recommended to use the ADIsimPower 2π × f × C C1 OUT1 tool to calculate compensation components. where fC1 is the crossover frequency.
Boost Regulator
To solve for RC1, use the following equation: The boost converter produces an undesirable right half plane 2 zero in the regulation feedback loop. This feedback loop requires 2π × f ×C ×(V ) C1 OUT1 POS R = compensating the regulator such that the crossover frequency C1 V ×V ×G ×G FB1 IN M1 CS1 occurs well below the frequency of the right half plane zero. The right half plane zero is determined by the fol owing equation: where GCS1 = 12.5 A/V. R 1 ( − DUTY )2 Using typical values for VFB1 and GM1 results in f (RHP 1 LOAD1 ) = Z1 π 2 ×L1 2094 × f ×C ×(V 2) C1 OUT1 POS R = where: C1 VIN fZ1(RHP) is the right half plane zero frequency. R For better accuracy, it is recommended to use the value of output LOAD1 is the equivalent load resistance or the output voltage divided by the load current. capacitance, COUT1, expected for the dc bias conditions under which it operates under in the calculation for RC1. V −V + DI V ODE1  DUT After the compensation resistor is known, set the zero formed 1 Y =  POS IN     PO V S + DI V ODE1  by the compensation capacitor and resistor to one-fourth of the crossover frequency, or where VDIODE1 is the forward voltage drop of the Schottky diode (D1). C = 2 C1 To stabilize the regulator, ensure that the regulator crossover π × f × R C1 C1 frequency is less than or equal to one-tenth of the right half where CC1 is the compensation capacitor value. plane zero frequency.
ERROR AMPLIFIER
The boost regulator loop gain is
FB1 COMP1 gM1
V V FB1 IN A = × × G × R ||Z × G × Z
REF1 R
VL1 M1 OUT1 COMP1 CS1 OUT1
C1
V V
CB1
POS POS
CC1
where: 044 A 12069- VL1 is the loop gain. V Figure 45. Compensation Components FB1 is the feedback regulation voltage VPOS is the regulated positive output voltage. The capacitor, CB1, is chosen to cancel the zero introduced by VIN is the input voltage. the output capacitor ESR. Solve for CB1 as follows: GM1 is the error amplifier transconductance gain. ESR × C R OUT1 OUT1 is the output impedance of the error amplifier and is 33 MΩ. CB1 = Z R COMP1 is the impedance of the series RC network from C1 COMP1 to AGND. Rev. E | Page 20 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide