Datasheet RX65N, RX651 Groups (Renesas) - 210
| 制造商 | Renesas |
| 描述 | 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory |
| 页数 / 页 | 246 / 210 — Figure 5.59. RMII Reception Timing (Error Occurrence). Figure 5.60. WOL … |
| 文件格式/大小 | PDF / 2.8 Mb |
| 文件语言 | 英语 |
Figure 5.59. RMII Reception Timing (Error Occurrence). Figure 5.60. WOL Output Timing (RMII). Figure 5.61
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文件文字版本
RX65N Group, RX651 Group 5. Electrical Characteristics REF50CK RMII0_CRS_DV RMII0_RXD1, Preamble SFD DATA xxxx RMII0_RXD0 Thd Tsu RMII0_RX_ER
Figure 5.59 RMII Reception Timing (Error Occurrence)
REF50CK tWOLd ET0_WOL
Figure 5.60 WOL Output Timing (RMII)
ET0_TX_CLK tTENd ET0_TX_EN tMTDd ET0_ETXD[3:0] Preamble SFD DATA CRC ET0_TX_ER tCRSs tCRSh ET0_CRS ET0_COL
Figure 5.61 MII Transmission Timing (Normal Operation)
R01DS0276EJ0230 Rev.2.30 Page 210 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
Figure 5.59 RMII Reception Timing (Error Occurrence)
REF50CK tWOLd ET0_WOL
Figure 5.60 WOL Output Timing (RMII)
ET0_TX_CLK tTENd ET0_TX_EN tMTDd ET0_ETXD[3:0] Preamble SFD DATA CRC ET0_TX_ER tCRSs tCRSh ET0_CRS ET0_COL
Figure 5.61 MII Transmission Timing (Normal Operation)
R01DS0276EJ0230 Rev.2.30 Page 210 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice