Datasheet AD9674 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | Octal Ultrasound AFE |
| 页数 / 页 | 47 / 4 — AD9674. Data Sheet. SPECIFICATIONS AC SPECIFICATIONS. Table 1. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 992 Kb |
| 文件语言 | 英语 |
AD9674. Data Sheet. SPECIFICATIONS AC SPECIFICATIONS. Table 1. Parameter2. Test Conditions/Comments. Min. Typ. Max. Unit
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AD9674 Data Sheet SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), fIN = 5 MHz, local oscil ator (LO) band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, programmable gain amplifier (PGA) gain = 27 dB, analog gain control, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 in Mode I1/Mode II,1 AAF LPF cutoff = fSAMPLE/4.5 in Mode III1/Mode IV,1 HPF cutoff = LPF cutoff/12.00, Mode I1 = fSAMPLE = 40 MSPS, Mode II1 = fSAMPLE = 65 MSPS, Mode III1 = fSAMPLE = 80 MSPS, Mode IV1 = fSAMPLE = 125 MSPS, RF decimator bypassed, digital filter bypassed, and low power LVDS mode, unless otherwise noted. Al gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).1
Table 1. Parameter2 Test Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential output 15.6/17.9/21.63 dB Single-ended input to single-ended 9.6/11.9/15.63 dB output 0.1 dB Input Compression Point LNA gain = 15.6 dB 1.00 V p-p LNA gain = 17.9 dB 0.75 V p-p LNA gain = 21.6 dB 0.45 V p-p 1 dB Input Compression Point LNA gain = 15.6 dB 1.20 V p-p LNA gain = 17.9 dB 0.90 V p-p LNA gain = 21.6 dB 0.60 V p-p Input Common Mode (LI-x, LG-x) 2.2 V Output Common Mode (LO-x) Switch off High-Z Ω Switch on 1.5 V Output Common Mode (LOSW-x) Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 300 Ω 50 Ω RFB = 1350 Ω 200 Ω RFB = ∞ (unterminated) 6 kΩ Input Capacitance (LI-x) 20 pF Input Referred Noise Voltage RS = 0 Ω LNA gain = 15.6 dB 0.83 nV/√Hz LNA gain = 17.9 dB 0.82 nV/√Hz LNA gain = 21.6 dB 0.78 nV/√Hz Input SNR Noise bandwidth = 15 MHz, 94 dB LNA gain = 21.6 dB Input Referred Noise Current 2.6 pA/√Hz FULL CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Cutoff −3 dB, programmable, low band mode 8 18 MHz −3 dB, programmable, high band mode 13.5 30 MHz In Range AAF Bandwidth Tolerance ±10 % Group Delay Variation f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V ±350 ps Input Referred Noise Voltage LNA gain = 15.6 dB 0.96 nV/√Hz LNA gain = 17.9 dB 0.90 nV/√Hz LNA gain = 21.6 dB 0.82 nV/√Hz Noise Figure RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 150 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 200 Ω 4.8 dB LNA gain = 21.6 dB, RFB = 300 Ω 3.8 dB Unterminated LNA gain = 15.6 dB 3.2 dB LNA gain = 17.9 dB 2.9 dB LNA gain = 21.6 dB 2.6 dB Correlated Noise Ratio No signal, correlated/uncorrelated −30 dB Rev. A | Page 4 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE
AD9674 Data Sheet SPECIFICATIONS AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), fIN = 5 MHz, local oscil ator (LO) band mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = midhigh, programmable gain amplifier (PGA) gain = 27 dB, analog gain control, VGAIN = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 in Mode I1/Mode II,1 AAF LPF cutoff = fSAMPLE/4.5 in Mode III1/Mode IV,1 HPF cutoff = LPF cutoff/12.00, Mode I1 = fSAMPLE = 40 MSPS, Mode II1 = fSAMPLE = 65 MSPS, Mode III1 = fSAMPLE = 80 MSPS, Mode IV1 = fSAMPLE = 125 MSPS, RF decimator bypassed, digital filter bypassed, and low power LVDS mode, unless otherwise noted. Al gain setting options are listed, which can be configured via SPI registers, and all power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).1
Table 1. Parameter2 Test Conditions/Comments Min Typ Max Unit
LNA CHARACTERISTICS Gain Single-ended input to differential output 15.6/17.9/21.63 dB Single-ended input to single-ended 9.6/11.9/15.63 dB output 0.1 dB Input Compression Point LNA gain = 15.6 dB 1.00 V p-p LNA gain = 17.9 dB 0.75 V p-p LNA gain = 21.6 dB 0.45 V p-p 1 dB Input Compression Point LNA gain = 15.6 dB 1.20 V p-p LNA gain = 17.9 dB 0.90 V p-p LNA gain = 21.6 dB 0.60 V p-p Input Common Mode (LI-x, LG-x) 2.2 V Output Common Mode (LO-x) Switch off High-Z Ω Switch on 1.5 V Output Common Mode (LOSW-x) Switch off High-Z Ω Switch on 1.5 V Input Resistance (LI-x) RFB = 300 Ω 50 Ω RFB = 1350 Ω 200 Ω RFB = ∞ (unterminated) 6 kΩ Input Capacitance (LI-x) 20 pF Input Referred Noise Voltage RS = 0 Ω LNA gain = 15.6 dB 0.83 nV/√Hz LNA gain = 17.9 dB 0.82 nV/√Hz LNA gain = 21.6 dB 0.78 nV/√Hz Input SNR Noise bandwidth = 15 MHz, 94 dB LNA gain = 21.6 dB Input Referred Noise Current 2.6 pA/√Hz FULL CHANNEL (TGC) CHARACTERISTICS AAF Low-Pass Cutoff −3 dB, programmable, low band mode 8 18 MHz −3 dB, programmable, high band mode 13.5 30 MHz In Range AAF Bandwidth Tolerance ±10 % Group Delay Variation f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V ±350 ps Input Referred Noise Voltage LNA gain = 15.6 dB 0.96 nV/√Hz LNA gain = 17.9 dB 0.90 nV/√Hz LNA gain = 21.6 dB 0.82 nV/√Hz Noise Figure RS = 50 Ω Active Termination Matched LNA gain = 15.6 dB, RFB = 150 Ω 5.6 dB LNA gain = 17.9 dB, RFB = 200 Ω 4.8 dB LNA gain = 21.6 dB, RFB = 300 Ω 3.8 dB Unterminated LNA gain = 15.6 dB 3.2 dB LNA gain = 17.9 dB 2.9 dB LNA gain = 21.6 dB 2.6 dB Correlated Noise Ratio No signal, correlated/uncorrelated −30 dB Rev. A | Page 4 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE