Datasheet AD4003-KGD (Analog Devices) - 5

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Known Good Die AD4003-KGD Parameter Test Conditions/Comments Min Typ Max Unit
Energy per Conversion 8 nJ/ sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested.
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency fS = 2 MSPS.
Table 2. Digital Interface Timing Parameter Symbol Min Typ Max Unit
CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE tCONV 270 290 320 ns ACQUISITION PHASE1 tACQ 290 ns TIME BETWEEN CONVERSIONS tCYC 500 ns CNV PULSE WIDTH (CS MODE)2 tCNVH 10 ns SCK PERIOD (CS MODE)3 tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK PERIOD (DAISY-CHAIN MODE)4 tSCK VIO > 2.7 V 20 ns VIO > 1.7 V 25 ns SCK LOW TIME tSCKL 3 ns SCK HIGH TIME tSCKH 3 ns SCK FALLING EDGE TO DATA REMAINS VALID DELAY tHSDO 1.5 ns SCK FALLING EDGE TO DATA VALID DELAY tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV OR SDI LOW TO SDO D17 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY5 tQUIET2 60 ns CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tDIS 20 ns SDI VALID SETUP TIME FROM CNV RISING EDGE tSSDICNV 2 ns SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tHSDICNV 2 ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV 12 ns SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tSSDISCK 2 ns SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSDISCK 2 ns 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. Rev. 0 | Page 5 of 9 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide