Datasheet AD4000, AD4004, AD4008 (Analog Devices) - 19
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 500 kSPS, Precision, Pseudo Differential, SAR ADC |
| 页数 / 页 | 36 / 19 — Data Sheet. AD4000/. AD4004/. AD4008. APPLICATIONS INFORMATION TYPICAL … |
| 修订版 | C |
| 文件格式/大小 | PDF / 1.4 Mb |
| 文件语言 | 英语 |
Data Sheet. AD4000/. AD4004/. AD4008. APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS. V+ ≥ +6.5V. REF1. LDO. 1.8V. AMP. VCM = VREF/2
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Data Sheet AD4000/ AD4004/ AD4008 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS
Figure 34 shows a recommended connection diagram when Figure 33 shows an example of the recommended connection using a single-supply system. This setup is preferable when only diagram for the AD4000/AD4004/AD4008 when multiple a limited number of rails are available in the system and power supplies are available. This configuration is used for best dissipation is of critical importance. performance because the amplifier supplies can be selected to allow the maximum signal range.
V+ ≥ +6.5V REF1 LDO 1.8V AMP VCM = VREF/2 5V 10kΩ 100nF 100nF 1.8V TO 5V HOST 10kΩ SUPPLY V+ 10µF R V AMP REF VCM = VREF/2 C REF VDD VIO 0V IN+ SDI V– AD4000/ SCK AD4004/ DIGITAL HOST (MICROPROCESSOR/ AD4008 SDO FPGA) IN– CNV GND 3-WIRE/4-WIRE INTERFACE
008
V– ≤ –0.5V
14956- Figure 33. Typical Application Diagram with Multiple Supplies
V+ = 5V REF1 LDO AMP VCM = VREF/2 4.096V 1.8V 10kΩ 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF1 10kΩ R 0.9 × V AMP REF VCM = VREF/2 C REF VDD VIO 0.1 × VREF IN+ SDI AD4000/ SCK 3 AD4004/ DIGITAL HOST (MICROPROCESSOR/ AD40082 SDO FPGA) IN– CNV GND 3-WIRE/4-WIRE INTERFACE 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).
009
2SPAN COMPRESSION MODE ENABLED. 3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.
14956- Figure 34. Typical Application Diagram with a Single Supply Rev. C | Page 19 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4000/AD4004/AD4008 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD4000/ AD4004/ AD4008 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS
Figure 34 shows a recommended connection diagram when Figure 33 shows an example of the recommended connection using a single-supply system. This setup is preferable when only diagram for the AD4000/AD4004/AD4008 when multiple a limited number of rails are available in the system and power supplies are available. This configuration is used for best dissipation is of critical importance. performance because the amplifier supplies can be selected to allow the maximum signal range.
V+ ≥ +6.5V REF1 LDO 1.8V AMP VCM = VREF/2 5V 10kΩ 100nF 100nF 1.8V TO 5V HOST 10kΩ SUPPLY V+ 10µF R V AMP REF VCM = VREF/2 C REF VDD VIO 0V IN+ SDI V– AD4000/ SCK AD4004/ DIGITAL HOST (MICROPROCESSOR/ AD4008 SDO FPGA) IN– CNV GND 3-WIRE/4-WIRE INTERFACE
008
V– ≤ –0.5V
14956- Figure 33. Typical Application Diagram with Multiple Supplies
V+ = 5V REF1 LDO AMP VCM = VREF/2 4.096V 1.8V 10kΩ 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF1 10kΩ R 0.9 × V AMP REF VCM = VREF/2 C REF VDD VIO 0.1 × VREF IN+ SDI AD4000/ SCK 3 AD4004/ DIGITAL HOST (MICROPROCESSOR/ AD40082 SDO FPGA) IN– CNV GND 3-WIRE/4-WIRE INTERFACE 1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R).
009
2SPAN COMPRESSION MODE ENABLED. 3SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION.
14956- Figure 34. Typical Application Diagram with a Single Supply Rev. C | Page 19 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4000/AD4004/AD4008 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE