Datasheet AD4002, AD4006, AD4010 (Analog Devices) - 34

制造商Analog Devices
描述18-Bit, 500 kSPS Precision Pseudo Differential SAR ADC
页数 / 页37 / 34 — AD4002/. AD4006/. AD4010. Data Sheet. DAISY-CHAIN MODE. CONVERT. CNV. …
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AD4002/. AD4006/. AD4010. Data Sheet. DAISY-CHAIN MODE. CONVERT. CNV. DIGITAL HOST. SDI. SDO. DATA IN. DEVICE A. DEVICE B. SCK. CLK. SDIA = 0. tCYC. tACQ

AD4002/ AD4006/ AD4010 Data Sheet DAISY-CHAIN MODE CONVERT CNV DIGITAL HOST SDI SDO DATA IN DEVICE A DEVICE B SCK CLK SDIA = 0 tCYC tACQ

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AD4002/ AD4006/ AD4010 Data Sheet DAISY-CHAIN MODE
the daisy-chain outputs its data MSB first, and 18 × N clocks are Use this mode to daisy-chain multiple AD4002/AD4006/AD4010 required to read back the N ADCs. The data is valid on both devices on a 3-wire or 4-wire serial interface. This feature is SCK edges. The maximum conversion rate is reduced because of useful for reducing component count and wiring connections, the total readback time. for example, in isolated multiconverter applications or for It is possible to write to each ADC register in daisy-chain mode. systems with a limited interfacing capacity. Data read back is The timing diagram is shown in Figure 49. This mode requires analogous to clocking a shift register. 4-wire operation because data is clocked in on the SDI line with A connection diagram example using two AD4002/AD4006/ CNV held low. The same command byte and register data can AD4010 devices is shown in Figure 63, and the corresponding be shifted through the entire chain to program al ADCs in the timing diagram is shown in Figure 64. chain with the same register contents, which requires 8 × (N + 1) clocks for N ADCs. It is possible to write different register contents When SDI and CNV are low, SDO is driven low. With SCK low, to each ADC in the chain by writing to the furthest ADC in the a rising edge on CNV initiates a conversion, selects daisy-chain chain, first using 8 × (N + 1) clocks, and then the second furthest mode, and disables the busy indicator. In this mode, CNV is ADC with 8 × N clocks, and so forth until reaching the nearest held high during the conversion phase and the subsequent data ADC in the chain, which requires 16 clocks for the command readback. and register data. It is not possible to read register contents in When the conversion is complete, the MSB is output onto SDO daisy-chain mode; however, the six status bits can be enabled if and the AD4002/AD4006/AD4010 enter the acquisition phase the user wants to determine the ADC configuration. Note that and power down. The remaining data bits stored in the internal enabling the status bits requires six extra clocks to clock out the shift register are clocked out of SDO by subsequent SCK falling ADC result and the status bits per ADC in the chain. Turbo edges. For each ADC, SDI feeds the input of the internal shift mode cannot be used in daisy-chain mode. register and is clocked by the SCK rising edges. Each ADC in
CONVERT CNV CNV DIGITAL HOST AD4002/ AD4002/ AD4006/ AD4006/ SDI SDO SDI SDO DATA IN AD4010 AD4010 DEVICE A DEVICE B SCK SCK
062
CLK
16233- Figure 63. Daisy-Chain Mode, Connection Diagram
SDIA = 0 tCYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tSCK tSCKL tQUIET2 tQUIET2 SCK 1 2 3 16 17 18 19 20 34 35 36 t tSSDISCK t HSCKCNV SCKH t t HSDISCK EN SDO D D A = SDIB A17 A16 DA15 DA1 DA0 tHSDO t t DIS DSDO
037
SDO DB17 DB16 DB15 D D D B1 DB0 A17 DA16 A1 DA0 B
16233- Figure 64. Daisy-Chain Mode, Serial Interface Timing Diagram Rev. 0 | Page 34 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4002/AD4006/AD4010 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE