Datasheet AK5704 (Asahi Kasei Microdevices) - 99
| 制造商 | Asahi Kasei Microdevices |
| 描述 | Low-Power 4-ch 32-bit ADC with MIC-Amp |
| 页数 / 页 | 109 / 99 — 11.1.3. PLL Slave Mode (MCKI pin) |
| 文件格式/大小 | PDF / 4.5 Mb |
| 文件语言 | 英语 |
11.1.3. PLL Slave Mode (MCKI pin)
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[AK5704]
11.1.3. PLL Slave Mode (MCKI pin)
Power Supply Example: (1) Audio I/F Format: I2S, 24-bit ≥1ms PLL Reference Clock: MCKI (12MHz) PDN pin MCKO: Enable (256fs) BCLK Frequency: 64fs VDD12 pin Sampling Frequency: 48kHz (2) (1) Power Supply & PDN pin = “L” “H” Flow Control ≥1ms (Addr:00H) (2) Addr:00H, Data:47H PMVCM bit Addr:01H, Data:80H (Addr:01H, D7) Addr:08H, Data:0AH Clock Mode Select Addr:09H, Data:10H (Addr:08H) Addr:0AH, Data:00H Addr:0BH, Data:18H PLL CLK Source Select Addr:0CH, Data:00H (Addr:09H) Addr:0DH, Data:7FH Addr:0EH, Data:00H PLL Ref CLK Divider 1, 2 (Addr:0AH, 0BH) PLL FB CLK Divider 1, 2 (3)Addr:01H, Data:C0H (Addr:0CH, 0DH) Audio I/F Format (4)MCKI Input (Addr:0EH) (3) PMPLL bit ≥ 5ms (Addr:01H, D6) MCKO output start (4) MCKI pin Input BCLK and LRCK input start 3ms (max) (5) MCKO pin (6) Output (7) BCLK pin Input LRCK pin Figure 60. Clock Set Up Sequence (3) <Sequence> (1) After power Up: PDN pin “L” → “H” “L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms or more is needed to power up VDD12. (2) Power Up VCOM and VREF: PMVCM bit = “0” → “1” PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, PLS, PLLMD, MCKOE, PLD[15:0], PLM[15:0], DIF[1:0], TDM[1:0], DLC[1:0], BCKP and SDTO2E bits must be set during this period. VCOM and VREF must first be powered-up before the other block operates. Power up time is 5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is 2.2μF ±50% each. (3) Power Up PLL: PMPLL bit = “0” → “1” (4) PLL starts after PMPLL bit changes from “0” to “1” and PLL reference clock is supplied from MCKI pin. The time until PLL is locked and starts normal output is 3ms (max). (5) The normal clock is output from the MCKO pin after the PLL became stable. (6) The invalid frequency is output from the MCKO pin during this period. (7) BCLK and LRCK clocks must be synchronized with MCKO clock. 019000890-E-00 2019/02 - 99 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE
11.1.3. PLL Slave Mode (MCKI pin)
Power Supply Example: (1) Audio I/F Format: I2S, 24-bit ≥1ms PLL Reference Clock: MCKI (12MHz) PDN pin MCKO: Enable (256fs) BCLK Frequency: 64fs VDD12 pin Sampling Frequency: 48kHz (2) (1) Power Supply & PDN pin = “L” “H” Flow Control ≥1ms (Addr:00H) (2) Addr:00H, Data:47H PMVCM bit Addr:01H, Data:80H (Addr:01H, D7) Addr:08H, Data:0AH Clock Mode Select Addr:09H, Data:10H (Addr:08H) Addr:0AH, Data:00H Addr:0BH, Data:18H PLL CLK Source Select Addr:0CH, Data:00H (Addr:09H) Addr:0DH, Data:7FH Addr:0EH, Data:00H PLL Ref CLK Divider 1, 2 (Addr:0AH, 0BH) PLL FB CLK Divider 1, 2 (3)Addr:01H, Data:C0H (Addr:0CH, 0DH) Audio I/F Format (4)MCKI Input (Addr:0EH) (3) PMPLL bit ≥ 5ms (Addr:01H, D6) MCKO output start (4) MCKI pin Input BCLK and LRCK input start 3ms (max) (5) MCKO pin (6) Output (7) BCLK pin Input LRCK pin Figure 60. Clock Set Up Sequence (3) <Sequence> (1) After power Up: PDN pin “L” → “H” “L” time of 1ms or more is needed to reset the AK5704. After the PDN pin = “H”, wait time of 1ms or more is needed to power up VDD12. (2) Power Up VCOM and VREF: PMVCM bit = “0” → “1” PSW0N, PSW1N, FS[3:0], CM[1:0], MSN, PLS, PLLMD, MCKOE, PLD[15:0], PLM[15:0], DIF[1:0], TDM[1:0], DLC[1:0], BCKP and SDTO2E bits must be set during this period. VCOM and VREF must first be powered-up before the other block operates. Power up time is 5.0ms (max) when the capacitance of an external capacitor for the VCOM and the VREF pin is 2.2μF ±50% each. (3) Power Up PLL: PMPLL bit = “0” → “1” (4) PLL starts after PMPLL bit changes from “0” to “1” and PLL reference clock is supplied from MCKI pin. The time until PLL is locked and starts normal output is 3ms (max). (5) The normal clock is output from the MCKO pin after the PLL became stable. (6) The invalid frequency is output from the MCKO pin during this period. (7) BCLK and LRCK clocks must be synchronized with MCKO clock. 019000890-E-00 2019/02 - 99 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE