Datasheet LTC2358-16 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Buffered Octal, 16-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range |
| 页数 / 页 | 40 / 8 — ADC TIMING CHARACTERISTICS Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 3.3 Mb |
| 文件语言 | 英语 |
ADC TIMING CHARACTERISTICS Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. Note 4:. Note 13:. Note 5:. Note 14:. Note 6:. Note 15:. Note 7:
该数据表的模型线
文件文字版本
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ADC TIMING CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2:
All voltage values are with respect to GND. error for these SoftSpan ranges is the worst-case deviation of the first and
Note 3:
V last code transitions from ideal and includes the effect of offset error. For DDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage as described in the Pin Functions section. Do not connect this pin to any measured from 0.5LSB when the output code flickers between 0000 0000 external circuitry. 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
Note 4:
When these pin voltages are taken below V ranges is the worst-case deviation of the last code transition from ideal EE or above VCC, they will be clamped by internal diodes. This product can handle input currents and includes the effect of offset error. of up to 100mA below V
Note 13:
All specifications in dB are referred to a full-scale input in the EE or above VCC without latchup.
Note 5:
When these pin voltages are taken below GND or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OV the crosstalk injection signal amplitude. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD or OVDD without latchup. change in output voltage by the specified temperature range.
Note 6:
–16.5V ≤ V
Note 15:
When REFBUF is overdriven, the internal reference buffer must EE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V be disabled by setting REFIN = 0V. DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions.
Note 16:
IREFBUF varies proportionally with sample rate and the number of
Note 8:
Exceeding these limits on any channel may corrupt conversion active channels. results on other channels. Driving an analog input above V
Note 17:
Analog input buffer supply currents from I CC on any VCC and IVEE are channel up to 10mA will not affect conversion results on other channels. reduced outside the acquisition period. Refer to nap mode in Applications Driving an analog input below V Information section. EE may corrupt conversion results on other channels. Refer to Applications Information section for further details.
Note 18:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, Refer to Absolute Maximum Ratings section for pin voltage limits related and OVDD = 5.25V. to device reliability.
Note 19:
A tSCKI period of 10ns minimum allows a shift clock frequency of
Note 9:
VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps, up to 100MHz for rising edge capture. internal reference and buffer, true bipolar input signal drive in bipolar
Note 20:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs. SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless otherwise specified.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
CMOS Timings
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 235816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timings (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 235816 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
Rev A 8 For more information www.analog.com Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS
ADC TIMING CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 11:
Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is Maximum Rating condition for extended periods may affect device the offset voltage measured from –0.5LSB when the output code flickers reliability and lifetime. between 0000 0000 0000 0000 and 1111 1111 1111 1111. Full-scale
Note 2:
All voltage values are with respect to GND. error for these SoftSpan ranges is the worst-case deviation of the first and
Note 3:
V last code transitions from ideal and includes the effect of offset error. For DDLBYP is the output of an internal voltage regulator, and should only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, unipolar SoftSpan ranges 5, 4, and 1, zero-scale error is the offset voltage as described in the Pin Functions section. Do not connect this pin to any measured from 0.5LSB when the output code flickers between 0000 0000 external circuitry. 0000 0000 and 0000 0000 0000 0001. Full-scale error for these SoftSpan
Note 4:
When these pin voltages are taken below V ranges is the worst-case deviation of the last code transition from ideal EE or above VCC, they will be clamped by internal diodes. This product can handle input currents and includes the effect of offset error. of up to 100mA below V
Note 13:
All specifications in dB are referred to a full-scale input in the EE or above VCC without latchup.
Note 5:
When these pin voltages are taken below GND or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OV the crosstalk injection signal amplitude. DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below ground or above V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD or OVDD without latchup. change in output voltage by the specified temperature range.
Note 6:
–16.5V ≤ V
Note 15:
When REFBUF is overdriven, the internal reference buffer must EE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V be disabled by setting REFIN = 0V. DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions.
Note 16:
IREFBUF varies proportionally with sample rate and the number of
Note 8:
Exceeding these limits on any channel may corrupt conversion active channels. results on other channels. Driving an analog input above V
Note 17:
Analog input buffer supply currents from I CC on any VCC and IVEE are channel up to 10mA will not affect conversion results on other channels. reduced outside the acquisition period. Refer to nap mode in Applications Driving an analog input below V Information section. EE may corrupt conversion results on other channels. Refer to Applications Information section for further details.
Note 18:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V, Refer to Absolute Maximum Ratings section for pin voltage limits related and OVDD = 5.25V. to device reliability.
Note 19:
A tSCKI period of 10ns minimum allows a shift clock frequency of
Note 9:
VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 200ksps, up to 100MHz for rising edge capture. internal reference and buffer, true bipolar input signal drive in bipolar
Note 20:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs. SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless otherwise specified.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
CMOS Timings
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 235816 F01 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timings (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 235816 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
Rev A 8 For more information www.analog.com Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS CONVERTER CHARACTERISTICS DYNAMIC ACCURACY INTERNAL REFERENCE CHARACTERISTICS REFERENCE BUFFER CHARACTERISTICS DIGITAL INPUTS AND DIGITAL OUTPUTS POWER REQUIREMENTS POWER REQUIREMENTS ADC TIMING CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS CONFIGURATION TABLES FUNCTIONAL BLOCK DIAGRAM TIMING DIAGRAM APPLICATIONS INFORMATION BOARD LAYOUT PACKAGE DESCRIPTION REVISION HISTORY TYPICAL APPLICATION RELATED PARTS