Datasheet ADuM4137 (Analog Devices) - 12

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ADuM4137 Data Sheet Table 11. Truth Table (Positive Logic)1 VI+ Input VI− Input ASC FAULT DRIVER_FAULT UVLO_FAULT VDD1 State VDD2 State VOFF_SOFT VOUT_ON VOUT_OFF
Low High <9 V High High High Powered Powered Low Low High High Low <9 V High High High Powered Powered Low High Low High High <9 V High High High Powered Powered Low Low High Low Low <9 V High High High Powered Powered Low Low High X X >9 V High Low High Powered Powered Low High Low X X X Low X X Powered Powered High X Low3 X X X X Low X Powered Powered High3, 4 X X X X X X X Low Powered Powered High3 X X X X >9 V X X X Unpowered Powered Low High Low X X <9 V X X X Unpowered Powered Low Low High X X X X X X X Unpowered High-Z High-Z Low2 1 X means don’t care or unknown. 2 With an unpowered VDD2, the ADuM4137 tries to hold the IGBT gate voltage to a value of approximately 3 V to 5 V. 3 The NMOS on VOUT_OFF is off during soft shutdown until the GATE_SENSE pin reaches 2 V, then the VOUT_OFF NMOS turns on along with the Miller clamp. 4 The driver only goes into soft shutdown when an actual fault occurs, such as an overcurrent, gate low violation or an error correction code (ECC) error (see Table 12 for fault mapping).
Table 12. FAULT Pin Mapping Fault Conditions FAULT Pin DRIVER_FAULT Pin UVLO_FAULT Pin
TSD Low, Latch Assert Time B = 20 ms (typical) Don’t care or unknown Don’t care or unknown TSx_OT_FAULT Low, Latch Assert Time B = 20 ms (typical) Don’t care or unknown Don’t care or unknown Gate Low Low, Latch Assert Time C = 26 ms (typical) Low, Latch Assert Time C = Low, Latch Assert Time C = 26 ms (typical) 26 ms (typical) VDD2 UVLO Low, Latch Assert Time B = 20 ms (typical) Don’t care or unknown Low, Latch Assert Time A = 13 ms (typical) OCx Overcurrent Low, Latch Assert Time B = 20 ms (typical) Low, Latch Assert Time C = Don’t care or unknown 26 ms (typical) ECC Error Low, Latch Assert Time B = 20 ms (typical) Low, Latch Assert Time C = Don’t care or unknown 26 ms (typical) ASC Don’t care or unknown Low, Latch Assert Time C = Don’t care or unknown 26 ms (typical) DT_FAULT Don’t care or unknown Low, Latch Assert Time A = Don’t care or unknown 13 ms (typical) Rev. 0 | Page 12 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ELECTRICAL CHARACTERISTICS SPI TIMING SPECIFICATIONS SPI Timing Diagram PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION PCB LAYOUT SPI AND EEPROM OPERATION SPI Programming USER REGISTER MAP USER REGISTER BITS OFFSET_2[5:0] Bits GAIN_2[5:0] Bits OFFSET_1[5:0] Bits GAIN_1[5:0] Bits CONFIGURATION REGISTER BITS OT_FAULT_OP Bit OT_FAULT_SEL Bit OC_TIME_OP Bit OC_2LEV_OP Bit LOW_T_OP Bit OC_BLANK_OP Bit tBLANK[3:0] Bits ECC_OFF_OP Bit T_RAMP_OP Bit PWM_OSC CONTROL REGISTER BITS ECC2_DBL_ERR Bit ECC2_SNG_ERR Bit ECC1_DBL_ERR Bit ECC1_SNG_ERR Bit PROG_BUSY Bit SIM_TRIM Bit SPI SAFETY PROPAGATION DELAY RELATED PARAMETERS PROTECTION FEATURES Primary Side UVLO Fault Reporting Overcurrent Detection High Speed, Two-Level Turn Off Miller Clamp Thermal Shutdown ASC Pin Functionality Isolated Temperature Sensor Low Temperature Operation Mode FAULTB Pin DRIVER_FAULTB Pin UVLO_FAULTB Pin VDD2 UVLO Fault UVLO_FAULTB Fault, Gate Low Dead Time Control DRIVER_FAULTB Fault, Dead Time Fault Power Dissipation INSULATION LIFETIME DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS