X9418 Datasheet (Renesas)

制造商Renesas
描述Low Noise/Low Power/2-Wire Bus
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NOT RECOMMENDED FOR NEW DESIGNS. NO RECOMMENDED REPLACEMENT. contact our Technical Support Center at

X9418 Datasheet Renesas, 修订版: 2.00

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NOT RECOMMENDED FOR NEW DESIGNS
DATASHEET
NO RECOMMENDED REPLACEMENT contact our Technical Support Center at
X9418
1-888-INTERSIL or www.intersil.com/tsc
FN8194 Low Noise/Low Power/2-Wire Bus Dual Digitally Controlled Potentiometers Rev 2.00 October 12, 2006 (XDCP™)
FEATURES DESCRIPTION • Two potentiometers in one package
The X9418 integrates two digitally controlled
• 2-wire serial interface
potentiometers (XDCP) on a monolithic CMOS
• Register oriented format
integrated microcircuit.
—Direct Read/Write/Transfer Wiper Position —Store as many as Four Positions per
The digitally controlled potentiometer is implemented
Potentiometer
using 63 resistive elements in a series array. Between
• Power supplies
each element are tap points connected to the wiper
—V
terminal through switches. The position of the wiper on
CC = 2.7V to 5.5V —V+ = 2.7V to 5.5V
the array is controlled by the user through the 2-wire
—V– = -2.7V to -5.5V
bus interface. Each potentiometer has associated with
• Low power CMOS
it a volatile Wiper Counter Register (WCR) and 4
—Standby current < 1µA
nonvolatile Data Registers (DR0:DR3) that can be
—Ideal for Battery Operated Applications
directly written to and read by the user. The contents
• High reliability
of the WCR controls the position of the wiper on the
—Endurance–100,000 Data Changes per Bit per
resistor array through the switches. Power up recalls
Register
the contents of DR0 to the WCR.
—Register Data Retention–100 years
The XDCP can be used as a three-terminal
• 8-bytes of nonvolatile memory
potentiometer or as a two-terminal variable resistor in
• 2.5k , 10k resistor array
a wide variety of applications including control,
• Resolution: 64 taps each potentiometer
parameter adjustments, and signal processing.
• 24-pin plastic DIP, 24-lead TSSOP and 24-lead SOIC packages • Pb-Free plus anneal available (RoHS compliant) BLOCK DIAGRAM
VCC V+ R0 R1 V VSS V- Wiper H0/RH0 Counter Register R2 R3 (WCR) VL0/RL0 WP SCL VW0/RW0 SDA Interface A0 and Control A1 8 Circuitry A2 A3 V Data W1/RW1 R0 R1 Wiper VH1/RH1 Resistor Counter Array Register XDCP1 R2 R3 (WCR) VL1/RL1 FN8194 Rev 2.00 Page 1 of 20 October 12, 2006