Datasheet ADSP-SC582, ADSP-SC583, ADSP-SC584, ADSP-SC587, ADSP-SC589, ADSP-21583, ADSP-21584, ADSP-21587 (Analog Devices) - 164

ADSP-SC582/SC583/SC584/SC587/SC589/ADSP-21583/21584/21587 Ball No. Pin Name Ball No. Pin Name Ball No. Pin Name Ball No. Pin Name
H04 DMC0_A00 K05 VDD_INT M06 VDD_DMC P07 GND H05 VDD_INT K06 VDD_DMC M07 GND P08 GND H06 VDD_DMC K07 GND M08 GND P09 GND H07 VDD_DMC K08 GND M09 GND P10 GND H08 VDD_DMC K09 GND M10 GND P11 GND H09 VDD_DMC K10 GND M11 GND P12 GND H10 VDD_DMC K11 GND M12 GND P13 GND H11 VDD_DMC K12 GND M13 GND P14 GND H12 VDD_DMC K13 GND M14 GND P15 GND H13 VDD_DMC K14 GND M15 GND P16 GND H14 VDD_DMC K15 GND M16 GND P17 GND H15 VDD_DMC K16 GND M17 GND P18 VDD_EXT H16 VDD_DMC K17 GND M18 VDD_EXT P19 PF_10 H17 VDD_DMC K18 VDD_EXT M19 PE_08 P20 PF_08 H18 VDD_DMC K19 VDD_INT M20 PE_11 P21 PF_15 H19 VDD_INT K20 PD_15 M21 PF_03 P22 PF_12 H20 SYS_CLKOUT K21 PF_11 M22 PF_00 P23 PG_00 H21 PE_12 K22 PF_06 M23 PF_02 R01 SYS_XTAL1 H22 PE_05 K23 PE_10 N01 JTG_TMS R02 SYS_BMODE1 H23 PE_02 L01 PC_04 N02 JTG_TRST R03 SYS_BMODE2 J01 DMC0_A15 L02 PC_12 N03 SYS_HWRST R04 SYS_BMODE0 J02 DMC0_A10 L03 PC_07 N04 PC_03 R05 VDD_INT J03 DMC0_A08 L04 PC_10 N05 VDD_INT R06 VDD_EXT J04 PC_08 L05 VDD_INT N06 VDD_EXT R07 GND J05 VDD_INT L06 VDD_DMC N07 GND R08 GND J06 VDD_DMC L07 GND N08 GND R09 GND J07 GND L08 GND N09 GND R10 GND J08 GND L09 GND N10 GND R11 GND J09 GND L10 GND N11 GND R12 GND J10 GND L11 GND N12 GND R13 GND J11 GND L12 GND N13 GND R14 GND J12 GND L13 GND N14 GND R15 GND J13 GND L14 GND N15 GND R16 GND J14 GND L15 GND N16 GND R17 GND J15 GND L16 GND N17 GND R18 VDD_EXT J16 GND L17 GND N18 VDD_EXT R19 VDD_INT J17 GND L18 VDD_EXT N19 VDD_INT R20 PG_01 J18 VDD_EXT L19 VDD_INT N20 PE_15 R21 PG_05 J19 PD_03 L20 PE_03 N21 PF_04 R22 PG_04 J20 PD_07 L21 PF_09 N22 PF_05 R23 PF_13 J21 PF_14 L22 PE_09 N23 PF_07 T01 SYS_CLKIN1 J22 PF_01 L23 PE_14 P01 JTG_TDO T02 PB_15 J23 PE_07 M01 PC_01 P02 JTG_TDI T03 GND K01 DMC0_RESET M02 PC_05 P03 SYS_FAULT T04 PB_14 K02 PC_11 M03 PC_02 P04 JTG_TCK T05 VDD_INT K03 PC_06 M04 SYS_FAULT P05 VDD_INT T06 VDD_EXT K04 PC_09 M05 VDD_INT P06 VDD_EXT T07 GND Rev. B | Page 164 of 173 | December 2018 Document Outline System Features Memory Additional Features Table of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC58x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC58x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers (USTAT) Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict-Cache Branch Target Buffer/Branch Predictor Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant C ode (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Arm TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Ports (LP) ADC Control Module (ACM) Interface 3-Phase Pulse Width Modulator (PWM) Units Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support (10/100/1000 EMAC Only) Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) PCI Express (PCIe) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller Media Local Bus (Media LB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration FFT/IFFT Accelerator Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator Harmonic Analysis Engine (HAE) Sinus Cardinalis (SINC) Filter Digital Transmission Content Protection (DTCP) System Design Clock Management Reset Control Unit (RCU) Real-Time Clock (RTC) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC58x/ADSP-2158x Detailed Signal Descriptions 349-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 349-Ball CSP_BGA Package 529-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for the 529-Ball CSP_BGA Package ADSP-SC58x/ADSP-2158x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LP) Serial Ports (SPORT) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port SPI Port—Master Timing SPI Port—Slave Timing SPI Port—SPI Ready (SPIx_RDY) Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose I/O Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Pulse Width Modulator (PWM) Timing PWM — Medium Precision (MP) Mode Timing PWM — Heightened Precision (HP) Mode Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) PCI Express (PCIe) 10/100 EMAC Timing (ETH0 and ETH1) 10/100/1000 EMAC Timing (ETH0 Only) Sinus Cardinalis (SINC) Filter Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode Media LB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 349-Ball CSP_BGA ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 529-Ball CSP_BGA Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide