Datasheet MAT02 (Analog Devices)

制造商Analog Devices
描述Low Noise, Matched Dual Monolithic Transistor
页数 / 页12 / 1 — Low Noise, Matched. Dual Monolithic Transistor. MAT02. FEATURES. PIN …
修订版E
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Low Noise, Matched. Dual Monolithic Transistor. MAT02. FEATURES. PIN CONNECTION. Low Offset Voltage: 50. V max. TO-78

Datasheet MAT02 Analog Devices, 修订版: E

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a
Low Noise, Matched Dual Monolithic Transistor MAT02 FEATURES PIN CONNECTION Low Offset Voltage: 50

V max TO-78 Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/

Hz max (H Suffix) High Gain (hFE): 500 min at IC = 1 mA 300 min at IC = 1

A Excellent Log Conformance: rBE

0.3

Low Offset Voltage Drift: 0.1

V/

C max Improved Direct Replacement for LM194/394 NOTE Substrate is connected to case on TO-78 package. Substrate is normally connected to the most negative circuit potential, but can be floated. PRODUCT DESCRIPTION
The design of the MAT02 series of NPN dual monolithic tran- The MAT02 should be used in any application where low sistors is optimized for very low noise, low drift and low r noise is a priority. The MAT02 can be used as an input BE. Precision Monolithics’ exclusive Silicon Nitride “Triple- stage to make an amplifier with noise voltage of less than Passivation” process stabilizes the critical device parameters 1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog over wide ranges of temperature and elapsed time. Also, the high circuits, may use the excellent logging conformity of the current gain (h MAT02. Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The FE) of the MAT02 is maintained over a wide range of collector current. Exceptional characteristics of the MAT02 electrical characteristics approach those of an ideal MAT02 include offset voltage of 50 µV max (A/E grades) and transistor when operated over a collector current range of 1 µ 150 µV max F grade. Device performance is specified over the A to 10 mA. For applications requiring multiple devices full military temperature range as well as at 25°C. see MAT04 Quad Matched Transistor data sheet. Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the parasitic isolation junction created by the protection diodes. This results in complete isola- tion between the transistors.
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