Datasheet LTC6957-1, LTC6957-2, LTC6957-3, LTC6957-4 (Analog Devices) - 19

制造商Analog Devices
描述Low Phase Noise, Dual Output Buffer/Driver/Logic Converter
页数 / 页38 / 19 — APPLICATIONS INFORMATION. General Considerations. Input Interfacing. …
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APPLICATIONS INFORMATION. General Considerations. Input Interfacing. Figure 1

APPLICATIONS INFORMATION General Considerations Input Interfacing Figure 1

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LTC6957-1/LTC6957-2/ LTC6957-3/LTC6957-4
APPLICATIONS INFORMATION General Considerations
in the timing before the system performance is degraded. The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are Users are encouraged to keep this distinction in mind low noise, dual output clock buffers that are designed while designing the entire clocking signal chain before, for demanding, low phase noise applications. Properly during, and after the LTC6957. applied, they can preserve phase noise performance in
Input Interfacing
situations where alternative solutions would degrade the phase noise significantly. They are also useful as logic The input stage is the same for all versions of the LTC6957 converters. and is designed for low noise and ease of interfacing to sine-wave and small amplitude signals. Other logic types However, no buffer device is capable of removing or can interface directly, or with little effort since they pres- reducing phase noise present on an input signal. As with ent a smaller challenge for noise preservation. most low phase noise circuits, improper application of the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can Figure 1 shows a simplified schematic of the LTC6957 result in an increase in the phase noise through a variety input stage. The diodes are all for protection, both during of mechanisms. The information below will, hopefully, ESD events and to protect the low noise NPN devices from allow a designer to avoid such an outcome. being damaged by input overdrive. The LTC6957 is designed to be used with high perfor- The resistors are to bias the input stage at an optimal mance clock signals destined for driving the encode DC level, but they are too large to leave floating without inputs of ADCs or mixer inputs. Such clocks should not increasing the noise. Therefore, for low noise use, always be treated as digital signals. The beauty of digital logic is connect both inputs to a low AC impedance. A capacitor to that there is noise margin both in the voltage and the tim- ground/return is imperative on the unused input in single- ing, before any deleterious effects are noticed. In contrast, ended applications. high performance clock signals have no margin for error 2 V+ FILTA 1 FILTERS FILTB 6 1.8k 1.2k IN+ 3 IN– 4 1.2k 2mA 3.2k GND 5 6957 F01
Figure 1
6957fb For more information www.linear.com/LTC6957-1 19 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagrams Timing Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts