Datasheet ADP7183 (Analog Devices) - 18
| 制造商 | Analog Devices |
| 描述 | -300 mA, Ultralow Noise, High PSRR, Low Dropout Linear Regulator |
| 页数 / 页 | 19 / 18 — ADP7183. Data Sheet. PCB LAYOUT CONSIDERATIONS |
| 修订版 | B |
| 文件格式/大小 | PDF / 805 Kb |
| 文件语言 | 英语 |
ADP7183. Data Sheet. PCB LAYOUT CONSIDERATIONS
该数据表的模型线
文件文字版本
ADP7183 Data Sheet PCB LAYOUT CONSIDERATIONS
Place the input capacitor (CIN) as close as possible to the VIN and GND pins. Place the output capacitor (COUT) as close as possible to the VOUT and GND pins. Place bypass capacitors (CA and CREG) close to the respective pins (VA and VREG) and GND. Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. Connect the exposed pad to VIN. -060 897 12 Figure 54. Typical Board Layout, Top Side 059 897- 12 Figure 53. Evaluation Board 1 -06 7 89 12 Figure 55. Typical Board Layout, Bottom Side Rev. B | Page 18 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADJUSTABLE MODE OPERATION ENABLE PIN OPERATION START-UP TIME APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor CA and CAFB Capacitors Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
Place the input capacitor (CIN) as close as possible to the VIN and GND pins. Place the output capacitor (COUT) as close as possible to the VOUT and GND pins. Place bypass capacitors (CA and CREG) close to the respective pins (VA and VREG) and GND. Use of 0805 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where area is limited. Connect the exposed pad to VIN. -060 897 12 Figure 54. Typical Board Layout, Top Side 059 897- 12 Figure 53. Evaluation Board 1 -06 7 89 12 Figure 55. Typical Board Layout, Bottom Side Rev. B | Page 18 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADJUSTABLE MODE OPERATION ENABLE PIN OPERATION START-UP TIME APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor CA and CAFB Capacitors Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE