Datasheet LTC1878 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | High Efficiency Monolithic Synchronous Step-Down Regulator |
| 页数 / 页 | 16 / 6 — PI FU CTIO S. RUN (Pin 1):. IN (Pin 6):. SYNC/MODE (Pin 7):. ITH (Pin … |
| 文件格式/大小 | PDF / 239 Kb |
| 文件语言 | 英语 |
PI FU CTIO S. RUN (Pin 1):. IN (Pin 6):. SYNC/MODE (Pin 7):. ITH (Pin 2):. VFB (Pin 3):. PLL LPF (Pin 8):. GND (Pin 4):. SW (Pin 5):
该数据表的模型线
文件文字版本
LTC1878
U U U PI FU CTIO S RUN (Pin 1):
Run Control Input. Forcing this pin below connects to the drains of the internal main and synchro- 0.4V shuts down the LTC1878. In shutdown all functions nous power MOSFET switches. are disabled drawing < 1µA supply current. Forcing this
V
pin above 1.2V enables the LTC1878. Do not leave RUN
IN (Pin 6):
Main Supply Pin. Must be closely decoupled to GND, Pin 4. floating.
SYNC/MODE (Pin 7):
External Clock Synchronization and
ITH (Pin 2):
Error Amplifier Compensation Point. The Mode Select Input. To synchronize with an external clock, current comparator threshold increases with this control apply a clock with a frequency between 400kHz and voltage. Nominal voltage range for this pin is from 0.5V 700kHz. To select Burst Mode operation, tie to V to 1.9V. IN. Ground- ing this pin selects pulse skipping mode. Do not leave this
VFB (Pin 3):
Feedback Pin. Receives the feedback voltage pin floating. from an external resistive divider across the output.
PLL LPF (Pin 8):
Output of the Phase Detector and Control
GND (Pin 4):
Ground Pin. Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If
SW (Pin 5):
Switch Node Connection to Inductor. This pin unused, this pin may be left open.
U U W FU CTIO AL DIAGRA
VIN BURST Y = “0” ONLY WHEN X IS A CONSTANT “1” Y DEFEAT X PLL LPF 8 SLOPE SYNC/MODE COMP 7 0.8V VCO OSC 0.6V – FREQ 6 VIN 3 + SHIFT – VFB + – EN SLEEP V + REF 6Ω 0.8V 0.55V + – + I – EA COMP BURST VIN SLEEP Ω S Q gm = 0.5m VIN R Q SWITCHING V 2 ITH RS LATCH IN LOGIC AND ANTI- SHOOT- RUN BLANKING CIRCUIT THRU 5 SW 1 0.8V REF – OVDET 0.85V + + SHUTDOWN IRCMP– 4 GND 1878 BD 6
U U U PI FU CTIO S RUN (Pin 1):
Run Control Input. Forcing this pin below connects to the drains of the internal main and synchro- 0.4V shuts down the LTC1878. In shutdown all functions nous power MOSFET switches. are disabled drawing < 1µA supply current. Forcing this
V
pin above 1.2V enables the LTC1878. Do not leave RUN
IN (Pin 6):
Main Supply Pin. Must be closely decoupled to GND, Pin 4. floating.
SYNC/MODE (Pin 7):
External Clock Synchronization and
ITH (Pin 2):
Error Amplifier Compensation Point. The Mode Select Input. To synchronize with an external clock, current comparator threshold increases with this control apply a clock with a frequency between 400kHz and voltage. Nominal voltage range for this pin is from 0.5V 700kHz. To select Burst Mode operation, tie to V to 1.9V. IN. Ground- ing this pin selects pulse skipping mode. Do not leave this
VFB (Pin 3):
Feedback Pin. Receives the feedback voltage pin floating. from an external resistive divider across the output.
PLL LPF (Pin 8):
Output of the Phase Detector and Control
GND (Pin 4):
Ground Pin. Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If
SW (Pin 5):
Switch Node Connection to Inductor. This pin unused, this pin may be left open.
U U W FU CTIO AL DIAGRA
VIN BURST Y = “0” ONLY WHEN X IS A CONSTANT “1” Y DEFEAT X PLL LPF 8 SLOPE SYNC/MODE COMP 7 0.8V VCO OSC 0.6V – FREQ 6 VIN 3 + SHIFT – VFB + – EN SLEEP V + REF 6Ω 0.8V 0.55V + – + I – EA COMP BURST VIN SLEEP Ω S Q gm = 0.5m VIN R Q SWITCHING V 2 ITH RS LATCH IN LOGIC AND ANTI- SHOOT- RUN BLANKING CIRCUIT THRU 5 SW 1 0.8V REF – OVDET 0.85V + + SHUTDOWN IRCMP– 4 GND 1878 BD 6