Datasheet LT1010 (Analog Devices) - 7

制造商Analog Devices
描述Fast ±150mA Power Buffer
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APPLICATIONS INFORMATION General. Design Concept. Supply Bypass. Equivalent Circuit

APPLICATIONS INFORMATION General Design Concept Supply Bypass Equivalent Circuit

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LT1010
APPLICATIONS INFORMATION General
idealized buffer with the unloaded gain specified for the These notes briefly describe the LT1010 and how it is LT1010. Otherwise, it has zero offset voltage, bias current used; a detailed explanation is given elsewhere.1 Emphasis and output resistance. Its output also saturates to the here will be on practical suggestions that have resulted internal supply terminals.2 from working extensively with the part over a wide range V+ of conditions. A number of applications are also outlined that demonstrate the usefulness of the buffer beyond that V + SOS of driving a heavy load. IB R′
Design Concept
VOS ROUT + INPUT A1 OUTPUT The schematic below describes the basic elements of the buffer design. The op amp drives the output sink transistor, R′ R′ = RSAT – ROUT Q3, such that the collector current of the output follower, V – SOS Q2, never drops below the quiescent value (determined by V– 1010 AI02 I1 and the area ratio of D1 and D2). As a result, the high frequency response is essentially that of a simple follower Loaded voltage gain can be determined from the unloaded even when Q3 is supplying the load current. The internal gain, AV , the output resistance, ROUT, and the load resis- feedback loop is isolated from the effects of capacitive tance, RL, using: loading by a small resistor in the output lead. A A VRL VL = V+ ROUT +RL D1 D2 BIAS Maximum positive output swing is given by: – + I2 (V+ – V Q2 V + = SOS+ )RL A1 OUT R Q1 INPUT SAT + RL R1 I1 OUTPUT The input swing required for this output is: Q3  R  V– V + = V + 1+ OUT 1010 AI01 IN OUT  RL  – VOS + ∆VOS The scheme is not perfect in that the rate of rise of sink current is noticeably less than for source current. This where ∆VOS is the 100mV clipping specified for the satu- can be mitigated by connecting a resistor between the ration measurements. Negative output swing and input bias terminal and V+, raising quiescent current. A feature drive requirements are similarly determined. of the final design is that the output resistance is largely independent of the follower quiescent current or the output
Supply Bypass
load current. The output will also swing to the negative rail, The buffer is no more sensitive to supply bypassing than which is particularly useful with single supply operation. slower op amps as far as stability is concerned. The 0.1µF disc ceramic capacitors usually recommended for
Equivalent Circuit
op amps are certainly adequate for low frequency work. Below 1MHz, the LT1010 is quite accurately represented As always, keeping the capacitor leads short and using by the equivalent circuit shown here for both small- and 1R. J. Widlar, “Unique IC Buffer Enhances Op Amp Designs; Tames Fast Amplifiers,” large-signal operation. The internal element, A1, is an Linear Technology Corp. TP-1, April, 1984. 2See electrical characteristics section for guaranteed limits. 1010fe 7 Document Outline Fteatures Applications Description Typical Application Absolute Maximum Ratings Preconditioning Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Applications Information Schematic Diagram Definition Of Terms Package Description Revision History Related Parts