Datasheet ADE9000 (Analog Devices) - 8

ADE9000 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY VDD 2.97 3.3 3.63 V Power-on reset level is 2.4 V to 2.6 V Supply Current (VDD) Power Save Mode 0 (PSM0) 15 17 mA Normal mode 14.5 16.5 mA Normal mode, six ADCs enabled Power Save Mode 3 (PSM3) 90 300 nA Idle, VDD = 3.3 V, AVDD = 0 V, DVDD = 0 V 1 Enables implementation of IEC 61000-4-30 Class S. 2 Tested during device characterization.
TIMING CHARACTERISTICS Table 2. Parameter Symbol Min Typ Max Unit
SS to SCLK Edge tSS 10 ns SCLK Frequency fSCLK 20 MHz SCLK Low Pulse Width tSL 20 ns SCLK High Pulse Width tSH 20 ns Data Output Valid After SCLK Edge tDAV 20 ns Data Input Setup Time Before SCLK Edge tDSU 10 ns Data Input Hold Time After SCLK Edge tDHD 10 ns Data Output Fall Time tDF 10 ns Data Output Rise Time tDR 10 ns SCLK Fall Time tSF 10 ns SCLK Rise Time tSR 10 ns MISO Disable Time After SS Rising Edge tDIS 100 ns SS High After SCLK Edge tSFS 0 ns
SS tSS tSFS SCLK tSL tSH t t t SF SR DAV tDIS MISO MSB INTERMEDIATE BITS LSB tDF tDR INTERMEDIATE BITS MOSI MSB IN LSB IN tDSU
002
tDHD
15210- Figure 2. SPI Interface Timing Digram Rev. A | Page 8 of 72 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY TYPICAL APPLICATIONS CIRCUIT SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE ENERGY ERROR OVER FREQUENCY AND POWER FACTOR ENERGY LINEARITY REPEATABILITY RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY ENERGY AND RMS LINEARITY WITH INTEGRATOR ON ENERGY AND RMS ERROR OVER FREQUENCY WITH INTEGRATOR ON SIGNAL-TO-NOISE RATIO PERFORMANCE TEST CIRCUIT TERMINOLOGY THEORY OF OPERATION MEASUREMENTS Current Channel ADC_REDIRECT Multiplexer Current Channel Gain, xIGAIN IB Calculation Using ICONSEL High-Pass Filter Digital Integrator Phase Compensation Multipoint Phase and Gain Calibration Voltage Channel RMS and Power Measurements Total and Fundamental RMS Total and Fundamental Active Power Total and Fundamental Reactive Power Total and Fundamental Apparent Power No Load Detection, Energy Accumulation, and Power Accumulation Features No Load Detection Feature Energy Accumulation Power Accumulation Digital to Frequency Conversion—CFx Output Energy and Phase Selection Configuring the CFx Pulse Width CFx Pulse Sign Clearing the CFx Accumulator POWER QUALITY MEASUREMENTS Zero-Crossing Detection CF3/ZX Zero-Crossing Timeout Line Period Calculation Angle Measurement Phase Sequence Error Detection Fast RMS½ Measurement 10 Cycle RMS/12 Cycle RMS Dip and Swell Indication Overcurrent Indication Peak Detection Power Factor Total Harmonic Distortion (THD) Resampling 128 Points per Cycle Temperature WAVEFORM BUFFER INTERRUPTS/EVENTS ACCESSING ON-CHIP DATA SPI PROTOCOL OVERVIEW ADDITIONAL COMMUNICATION VERIFICATION REGISTERS CRC OF CONFIGURATION REGISTERS CONFIGURATION LOCK REGISTER MAP REGISTER DETAILS OUTLINE DIMENSIONS ORDERING GUIDE