Datasheet ATtiny28L, ATtiny28V (Atmel) - 47

ATtiny28L/V Programming the Flash
Atmel’s ATtiny28 offers 2K bytes of Flash program memory. The ATtiny28 is shipped with the on-chip Flash program memory array in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a high- voltage (12V) parallel programming mode. Only minor currents (<1mA) are drawn from the +12V pin during programming. The program memory array in the ATtiny28 is programmed byte-by-byte. During pro- gramming, the supply voltage must be in accordance with Table 21.
Table 21.
Supply Voltage during Programming
Part Serial Programming Parallel Programming
ATtiny28 Not applicable 4.5 - 5.5V
Parallel Programming
This section describes how to parallel program and verify Flash program memory, Lock bits and Fuse bits in the ATtiny28.
Signal Names
In this section, some pins of the ATtiny28 are referenced by signal names describing their function during parallel programming. See Figure 37 and Table 22. Pins not described in Table 22 are referenced by pin name. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi- tive pulse. The coding is shown in Table 23. When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different bits are assigned functions, as shown in Table 24.
Figure 37.
Parallel Programming
ATtiny28
+5V PD1 VCC RDY/BSY OE PD2 PB7 - PB0 DATA WR PD3 BS PD4 XA0 PD5 XA1 PD6 +12V RESET XTAL1 GND
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1062F–AVR–07/06 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA3..PA0) Port B (PB7..PB0) Port D (PD7..PD0) XTAL1 XTAL2 RESET Architectural Overview ALU - Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File Status Register Status Register - SREG System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock External RC Oscillator Register Description Oscillator Calibration Register - OSCCAL Memories I/O Memory Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction Memory Access and Instruction Execution Timing Flash Program Memory Sleep Modes Idle Mode Power-down Mode System Control and Reset Reset Sources Power-on Reset External Reset Watchdog Reset Register Description MCU Control and Status Register - MCUCS Interrupts Reset and Interrupt Interrupt Handling Interrupt Response Time External Interrupt Low-level Input Interrupt Register Description Interrupt Control Register - ICR Interrupt Flag Register - IFR I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 Port A Schematics Port B Port B as General Digital Input Alternate Functions of Port B Port B Schematics Port D Port D as General Digital I/O Register Description Port A Data Register - PORTA Port A Control Register - PACR Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port D Data Register - PORTD Port D Data Direction Register - DDRD Port D Input Pins Address - PIND Timer/Counter0 Timer/Counter Prescaler Register Description Timer/Counter0 Control Register - TCCR0 Timer Counter 0 - TCNT0 Watchdog Timer Register Description Watchdog Timer Control Register - WDTCR Hardware Modulator Register Description Modulation Control Register - MODCR Analog Comparator Register Description Analog Comparator Control and Status Register - ACSR Memory Programming Program Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash Parallel Programming Signal Names Enter Programming Mode Chip Erase Programming the Flash Reading the Flash Programming the Fuse Bits Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte Parallel Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics External Clock Drive Waveforms External Clock Drive Typical Characteristics Register Summary Instruction Set Summary Ordering Information Packaging Information 32A 28P3 32M1-A Errata All revisions Datasheet Revision History Rev - 01/06G Rev - 01/06G Rev - 03/05F Table of Contents