Datasheet KS8995XA (Microchip) - 10
| 制造商 | Microchip |
| 描述 | Integrated 5-Port 10/100 QoS Switch |
| 页数 / 页 | 55 / 10 |
| 文件格式/大小 | PDF / 361 Kb |
| 文件语言 | 英语 |
该数据表的模型线
文件文字版本
Micrel, Inc. KS8995XA Pin Number Pin Name Type(1) 31 VDDAR P 32 RXP5 I 5 Physical receive signal + (differential). 5 Physical receive signal – (differential). Port Pin Function(2)
1.8V analog VDD. 33 RXM5 I 34 GNDA Gnd 35 TXP5 O 5 Physical transmit signal + (differential). 36 TXM5 O 5 Physical transmit signal – (differential). 37 VDDAT P 38 FXSD5 I 5 Fiber signal detect/factory test pin. 39 FXSD4 I 4 Fiber signal detect/factory test pin. 40 GNDA Gnd 41 VDDAR P 42 GNDA Gnd 43 VDDAR P 44 GNDA Gnd 45 NC / MUX1 I No connect. Factory test pin. 46 NC / MUX2 I No connect. Factory test pin. 47 PWRDN_N Ipu 48 RESERVE/NC 49 GNDD Gnd 50 VDDC P 51 PMTXEN Ipd 5 PHY[5] MII transmit enable. 52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3. 53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2. 54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1. 55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0. 56 PMTXER Ipd 5 PHY[5] MII transmit error. 57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII. 58 GNDD Gnd 59 VDDIO P 60 PMRXC O Analog ground. 2.5V or 3.3V analog VDD. Analog ground.
1.8V analog VDD.
Analog ground.
1.8V analog VDD.
Analog ground. Full-chip power down. Active low.
Reserved pin. No connect.
Digital ground.
1.8V digital core VDD. Digital ground.
3.3V digital VDD for digital I/O circuitry.
5 PHY[5] MII receive clock. PHY mode MII. Notes:
1.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2.
PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated. September 2008 10 M9999-091508
1.8V analog VDD. 33 RXM5 I 34 GNDA Gnd 35 TXP5 O 5 Physical transmit signal + (differential). 36 TXM5 O 5 Physical transmit signal – (differential). 37 VDDAT P 38 FXSD5 I 5 Fiber signal detect/factory test pin. 39 FXSD4 I 4 Fiber signal detect/factory test pin. 40 GNDA Gnd 41 VDDAR P 42 GNDA Gnd 43 VDDAR P 44 GNDA Gnd 45 NC / MUX1 I No connect. Factory test pin. 46 NC / MUX2 I No connect. Factory test pin. 47 PWRDN_N Ipu 48 RESERVE/NC 49 GNDD Gnd 50 VDDC P 51 PMTXEN Ipd 5 PHY[5] MII transmit enable. 52 PMTXD3 Ipd 5 PHY[5] MII transmit bit 3. 53 PMTXD2 Ipd 5 PHY[5] MII transmit bit 2. 54 PMTXD1 Ipd 5 PHY[5] MII transmit bit 1. 55 PMTXD0 Ipd 5 PHY[5] MII transmit bit 0. 56 PMTXER Ipd 5 PHY[5] MII transmit error. 57 PMTXC O 5 PHY[5] MII transmit clock. PHY mode MII. 58 GNDD Gnd 59 VDDIO P 60 PMRXC O Analog ground. 2.5V or 3.3V analog VDD. Analog ground.
1.8V analog VDD.
Analog ground.
1.8V analog VDD.
Analog ground. Full-chip power down. Active low.
Reserved pin. No connect.
Digital ground.
1.8V digital core VDD. Digital ground.
3.3V digital VDD for digital I/O circuitry.
5 PHY[5] MII receive clock. PHY mode MII. Notes:
1.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
Ipd/O = Input w/internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/internal pull-up during reset, output pin otherwise.
2.
PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated. September 2008 10 M9999-091508