Datasheet KSZ8795CLX (Microchip) - 10

KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED) Pin Pin Type Port Description Number Name Note 2-1
62 LED2_1 Ipu/O 2 Port 2 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Port 5 GMII/MII and RMII mode select When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (Default) PD = GMII/MII is in GPHY/PHY mode.
Note:
When set GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output. When set MII to PHY mode, the CRS, COL, RXC and TXC pins will change from the input to output. When Port 5 is RMII mode: PU = Clock mode in RMII, using 25MHz OSC clock and provide 50 MHz RMII clock from pin RXC5. PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the port 5 RMII will receive an external 50 MHz clock
Note:
Port 5 also can use either an internal or external clock in RMII mode based on this strap pin or the set- ting of the Register 86 (0x56) bit[7]. 63 LED2_0 Ipu/O 2 Port 2 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: REFCLKO enable PU = REFCLK_O (25 MHz) is enabled. (Default) PD = REFCLK_O is disabled.
Note:
It is better to disable this 25 MHz clock if not provid- ing an extra 25 MHz clock for the system. 64 LED1_1 Ipu/O 1 Port 1 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: PLL Clock source select PU = Still use 25 MHz clock from XI/XO pin even though it is in Port 5 RMII normal mode. PD = Use external clock from pin TXC5 in Port 5 RMII normal mode.
Note:
If received clock in Port 5 RMII normal mode has large clock jitter, one can select the 25 MHz crystal/ oscillator as the switch’s clock source. 65 LED1_0 Ipu/O 1 Port 1 LED Indicator 0: See Global Register 11 bits [5:4] for details. Strap Option: Speed select in GMII/RGMII PU = 1Gbps in GMII/RGMII.(Default) PD = 10/100Mbps in GMII/RGMII.
Note:
Programmable through internal registers also. 66 SPIQ Ipd/O All SPI Serial Data Output in SPI Slave Mode: Strap Option: Serial bus configuration. PD = SPI slave mode. PU = MDC/MDIO mode.
Note:
An external pull-up or pull-down resistor is required. DS00002112B-page 10

 2016-2017 Microchip Technology Inc. Document Outline Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces 1.0 Introduction 1.1 General Description FIGURE 1-1: Functional Block Diagram 2.0 Pin Description and Configuration FIGURE 2-1: 80-LQFP Pin Assignment (TOP View) TABLE 2-1: Signals - KSZ8795CLX (Continued) TABLE 2-2: Strap-in Options - KSZ8795CLX (Continued) 3.0 Functional Description 3.1 Physical Layer (PHY) 3.1.1 100BASE-TX Transmit 3.1.2 100BASE-TX Receive 3.1.3 PLL Clock Synthesizer 3.1.4 Scrambler/De-Scrambler (100BASE-TX Only) 3.1.5 10BASE-T Transmit 3.1.6 10BASE-T Receive 3.1.7 MDI/MDI-X Auto Crossover TABLE 3-1: MDI/MDI-X Pin Definitions FIGURE 3-1: Typical Straight Cable Connection FIGURE 3-2: Typical Crossover Cable Connection 3.1.8 Auto-Negotiation FIGURE 3-3: Auto-Negotiation and PArallel Operation 3.1.9 LinkMD® Cable Diagnostics 3.1.10 On-Chip Termination and Internal Biasing 3.2 Media Access Controller (MAC) Operation 3.2.1 Inter-Packet Gap (IPG) 3.2.2 Backoff Algorithm 3.2.3 Late Collision 3.2.4 Illegal Frames 3.2.5 Flow Control 3.2.6 Half-Duplex Back Pressure 3.2.7 Broadcast Storm Protection 3.3 Switch Core 3.3.1 Address Look-Up 3.3.2 learning 3.3.3 Migration 3.3.4 Aging 3.3.5 Forwarding FIGURE 3-4: Destination Address Lookup and Resolution Flow Chart 3.3.6 Switching Engine 3.4 Power and Power Management TABLE 3-2: KSZ8795CLX Voltage Options and Requirements (Continued) TABLE 3-3: Internal Function Block Status 3.4.1 Normal Operation Mode 3.4.2 Energy Detect Mode 3.4.3 Soft Power-Down Mode 3.4.4 Port-Based Power-Down Mode 3.4.5 Energy Efficient Ethernet (EEE) FIGURE 3-5: IEEE Transmit and Receive Signaling Paths FIGURE 3-6: Traffic Activity and EEE LPI Operations 3.4.6 Wake-on-LAN (WoL) 3.4.7 Interrupt (INT_N/PME_N) 3.5 Interfaces TABLE 3-4: Available Interfaces 3.5.1 Configuration Interface TABLE 3-5: SPI Connections FIGURE 3-7: SPI Access Timing FIGURE 3-8: SPI Multiple Access Timing TABLE 3-6: MII Management Interface Frame Format (Note 3-1) 3.5.2 Switch Port 5 GMAC Interface TABLE 3-7: Signals of GMII/RGMII/MII/RMII TABLE 3-8: Port 5 SW5-MII Connection TABLE 3-9: Port 5 SW5-GMII Connection (Continued) TABLE 3-10: Port 5 SW5-RGMII Connection TABLE 3-11: Port 5 Sw5-RGMII Clock Delay Configuration with Connection Partner (Continued) TABLE 3-12: Port 5 SW5-RMII Connection 3.6 Advanced Functionality 3.6.1 QoS Priority Support FIGURE 3-9: 802.1p Priority field Format 3.6.2 Spanning Tree Support TABLE 3-13: Port Setting and Software Actions for Spanning Tree 3.6.3 Rapid Spanning Tree Support TABLE 3-14: Port Setting and Software Actions for Rapid Spanning Tree 3.6.4 Tail Tagging Mode FIGURE 3-10: Tail Tag Frame Format TABLE 3-15: Tail Tag Rules 3.6.5 IGMP Support 3.6.6 IPv6 MLD Snooping 3.6.7 Port Mirroring Support 3.6.8 VLAN Support TABLE 3-16: FID+DA Look-Up in VLAN Mode (Continued) TABLE 3-17: FID+SA Look-Up in VLAN Mode 3.6.9 Rate Limiting Support TABLE 3-18: 10/100/1000 Mbps Rate Selection for the Rate Limit (Continued) 3.6.10 VLAN and Address Filtering 3.6.11 802.1X Port-Based Security 3.6.12 ACL Filtering FIGURE 3-11: ACL Format 4.0 Device Registers FIGURE 4-1: Interface and Register Mapping TABLE 4-1: Mapping of Functional Areas within the Address Space (Continued) 4.1 Register Map TABLE 4-2: Direct Registers (Continued) TABLE 4-3: Global Registers (Continued) 4.2 Port Registers TABLE 4-4: Port Registers (Continued) 4.3 Advanced Control Registers TABLE 4-5: Advanced Control REgisters 104 - 109 TABLE 4-6: Advanced control Registers 110 - 111 (Continued) TABLE 4-7: ADvanced Control Registers 112 - 120 (Continued) TABLE 4-8: Advanced Control Registers 160, 124 - 127 (Continued) TABLE 4-9: Advanced Control Registers 128 - 129 (Continued) TABLE 4-10: Advanced Control Registers 130 - 135 (Continued) TABLE 4-11: Advanced Control Registers 144 - 159 (Continued) TABLE 4-12: Advanced Control REgisters 163 - 164 TABLE 4-13: Additional Advanced Control REgisters (Note 4-1) (Continued) TABLE 4-14: Advanced Control Registers 191 - 255 TABLE 4-15: Indirect Register Descriptions (Continued) 4.4 Static MAC Address Table TABLE 4-16: Static MAC Address Table (Continued) 4.5 VLAN Table TABLE 4-17: VLAN Table TABLE 4-18: VLAN ID and Indirect Registers (Continued) 4.6 Dynamic MAC Address Table TABLE 4-19: Dynamic MAC Address Table 4.7 PME Indirect Registers TABLE 4-20: PME Indirect Registers (Continued) 4.8 ACL Rule Table and ACL Indirect Registers 4.8.1 ACL Register and Programming Model FIGURE 4-2: ACL Table Access 4.8.2 ACL Indirect Registers TABLE 4-21: ACL Indirect Registers for 14 Byte ACL Rules (Continued) TABLE 4-22: Temporal Storage for 14 Bytes ACL RULES (Continued) TABLE 4-23: ACL Read/Write Control (Continued) 4.9 EEE Indirect Registers TABLE 4-24: EEE Global Registers (Continued) TABLE 4-25: EEE Port Registers (Continued) 4.10 Management Information Base (MIB) Counters TABLE 4-26: Port MIB Counter Indirect Memory Offsets (Continued) TABLE 4-27: Format of Per-Port MIB Counter TABLE 4-28: All Port Dropped Packet MIB Counters TABLE 4-29: Format of Per-Port Rx/Tx Total Bytes MIB Counter (in Table 4-28) TABLE 4-30: Format of All Dropped Packet MIB Counter (in Table 4-28) 4.11 MIIM Registers TABLE 4-31: MIIM Registers (Continued) 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics TABLE 6-1: Electrical Characteristics (Continued) 7.0 Timing Diagrams FIGURE 7-1: GMII Signals Timing Diagram TABLE 7-1: GMII Timing Parameters FIGURE 7-2: RGMII v2.0 Specification TABLE 7-2: RGMII Timing Parameters FIGURE 7-3: MAC Mode MII Timing - Data Received from MII FIGURE 7-4: MAC Mode MII Timing - Data Transmitted from MII TABLE 7-3: MAC Mode MII Timing Parameters FIGURE 7-5: PHY Mode MII Timing - Data Received from MII FIGURE 7-6: PHY Mode MII Timing - Data Transmitted from MII TABLE 7-4: PHY Mode MII Timing Parameters FIGURE 7-7: RMII TIming - Data Received from RMII FIGURE 7-8: RMII Timing - Data Transmitted from RMII TABLE 7-5: RMII Timing Parameters FIGURE 7-9: SPI Input Timing TABLE 7-6: SPI Input Timing Parameters FIGURE 7-10: SPI Output Timing TABLE 7-7: SPI Output Timing Parameters FIGURE 7-11: Auto-Negotiation Timing TABLE 7-8: Auto-Negotiation Timing Parameters FIGURE 7-12: MDC/MDIO Timing TABLE 7-9: MDC/MDIO Typical Timing Parameters FIGURE 7-13: Power-Down/Power-Up and Reset Timing TABLE 7-10: Reset Timing Parameters 8.0 Reset Circuit FIGURE 8-1: Recommended Reset Circuit FIGURE 8-2: Recommended Circuit for Interfacing with CPU/FPGA Reset 9.0 Selection of Isolation Transformer TABLE 9-1: 25 MHz Crystal/Reference Clock Selection Criteria TABLE 9-2: Qualified Magnetic Vendors 10.0 Selection of Reference Crystal TABLE 10-1: Typical Reference Crystal Characteristics 11.0 Package Outlines FIGURE 11-1: 80-Lead 10 mm x 10 mm LQFP Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service