Datasheet ADXRS450 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | ±300°/sec High Vibration Immunity Digital Gyro |
| 页数 / 页 | 29 / 8 — Data Sheet. ADXRS450. TYPICAL PERFORMANCE CHARACTERISTICS. TION. OF P. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 696 Kb |
| 文件语言 | 英语 |
Data Sheet. ADXRS450. TYPICAL PERFORMANCE CHARACTERISTICS. TION. OF P. –2.0. –1.6 –1.2. –0.8. –0.4. 0.4. 0.8. 1.2. 1.6. 2.0. –2. –1. –0
该数据表的模型线
文件文字版本
Data Sheet ADXRS450 TYPICAL PERFORMANCE CHARACTERISTICS 20 40 18 35 16 30 14 TION 25 12 TION LA LA U U 10 20 OP OP 8 OF P 15 OF P % 6 % 10 4 5 2 0 0 0 6 2 8 4 0 4 8 2 6 0
009 006
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –2. –1. –1. 0. 0. 1. 1. 2. –0. –0. NULL ERROR (°/sec)
08952-
NULL ERROR (°/sec)
08952- Figure 6. SOIC_CAV Null Error @ 25°C Figure 9. LCC_V Null Error @ 25°C
30 25 25 20 20 TION TION 15 A A L L U U 15 OP OP 10 OF P OF P 10 % % 5 5 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 20 18 16 14 12 10 08 06 04 02 02 04 06 08 10 12 14 16 18 20 22 0. 1. 1. 2. 2.
029
3.
007
0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. –3. –2. –2. –1. –1. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. CHANGE IN SENSITIVITY (%) NULL TEMPERATURE COEFFICIENT (°/sec/°C)
08952- 08952- Figure 7. SOIC_CAV Null Temperature Coefficient Figure 10. LCC_V Sensitivity Error @ 25°C
25 20 20 15 TION 15 TION A LA L U U 10 OP OP 10 OF P OF P % % 5 5 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0. 1. 1. 2. 2. 08 07 06 05 04 03 02 01 01 02 03 04 05 06 07 08 10 –3. –2. –2. –1. –1. –0. 3.
008 12 1
0. 0. 0. 0. 0. 0. 0. 0. 0. –0. –0. –0. –0. –0. –0. –0. –0. CHANGE IN SENSITIVITY (%)
08952-
SENSITIVITY DRIFT (%/°C)
08952- Figure 8. SOIC_CAV Sensitivity Error @ 25°C Figure 11. SOIC_CAV Sensitivity Drift over Temperature Rev. C | Page 7 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide
009 006
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0 –2. –1. –1. 0. 0. 1. 1. 2. –0. –0. NULL ERROR (°/sec)
08952-
NULL ERROR (°/sec)
08952- Figure 6. SOIC_CAV Null Error @ 25°C Figure 9. LCC_V Null Error @ 25°C
30 25 25 20 20 TION TION 15 A A L L U U 15 OP OP 10 OF P OF P 10 % % 5 5 0 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 20 18 16 14 12 10 08 06 04 02 02 04 06 08 10 12 14 16 18 20 22 0. 1. 1. 2. 2.
029
3.
007
0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. –3. –2. –2. –1. –1. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. –0. CHANGE IN SENSITIVITY (%) NULL TEMPERATURE COEFFICIENT (°/sec/°C)
08952- 08952- Figure 7. SOIC_CAV Null Temperature Coefficient Figure 10. LCC_V Sensitivity Error @ 25°C
25 20 20 15 TION 15 TION A LA L U U 10 OP OP 10 OF P OF P % % 5 5 0 0 0 5 0 5 0 5 0 5 0 5 0 5 0 0 0. 1. 1. 2. 2. 08 07 06 05 04 03 02 01 01 02 03 04 05 06 07 08 10 –3. –2. –2. –1. –1. –0. 3.
008 12 1
0. 0. 0. 0. 0. 0. 0. 0. 0. –0. –0. –0. –0. –0. –0. –0. –0. CHANGE IN SENSITIVITY (%)
08952-
SENSITIVITY DRIFT (%/°C)
08952- Figure 8. SOIC_CAV Sensitivity Error @ 25°C Figure 11. SOIC_CAV Sensitivity Drift over Temperature Rev. C | Page 7 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide