Datasheet ADXRS450 (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | ±300°/sec High Vibration Immunity Digital Gyro |
| 页数 / 页 | 29 / 3 — ADXRS450. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/13—Rev. B to … |
| 修订版 | C |
| 文件格式/大小 | PDF / 696 Kb |
| 文件语言 | 英语 |
ADXRS450. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 5/13—Rev. B to Rev. C. 12/11—Rev. A to Rev. B. 6/11—Rev. 0 to Rev. A
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ADXRS450 Data Sheet TABLE OF CONTENTS
Features .. 1 Mechanical Considerations for Mounting .. 10 Applications ... 1 Applications Circuits ... 10 General Description ... 1 ADXRS450 Signal Chain Timing ... 10 Functional Block Diagram .. 1 SPI Communication Protocol ... 12 Revision History ... 2 Command/Response ... 12 Specifications ... 3 SPI Communications Characteristics .. 13 Absolute Maximum Ratings .. 4 SPI Applications ... 14 Thermal Resistance .. 4 SPI Rate Data Format ... 19 Rate Sensitive Axis ... 4 Memory Map and Registers .. 20 ESD Caution .. 4 Memory Map .. 20 Pin Configuration and Function Descriptions ... 5 Memory Register Definitions ... 21 Typical Performance Characteristics ... 7 Package Orientation and Layout Information .. 23 Theory of Operation .. 9 Package Marking Codes .. 25 Continuous Self-Test .. 9 Outline Dimensions ... 26 Applications Information .. 10 Ordering Guide .. 27
REVISION HISTORY 5/13—Rev. B to Rev. C
Changes to Features Section.. 1 Changed Null Accuracy from ±3°/sec to ±6°/sec... 3 Deleted Figure 6 from Low-Pass Filter Cut-Off (−3 dB) Frequency Test Conditions/Comments and Figure 7 from ST Low-Pass Filter −3 dB Frequency Test Conditions/Comments. .. 3 Changes to Figure 6, Figure 7, and Figure 11 ... 7 Deleted Figure 10; Renumbered Sequentially... 7 Deleted Figure 13 and Figure 15 ... 8 Added Figure 12; Renumbered Sequentially .. 8 Changes to Figure 13 and Figure 15 ... 8 Deleted Calibrated Performance Section .. 10 Changes to Applications Circuits Section ... 11 Changes to Figure 25 .. 18 Changed Heading in Table 14 to 16-Bit Rate Data .. 19 Updated Outline Dimensions ... 26
12/11—Rev. A to Rev. B
Changes to the Rate Sensitive Axis Section .. 4 Changes to Figure 5 .. 6 Changes to Figure 28 .. 23 Deleted Figure 31, Renumbered Sequentially... 24 Changes to Back Side Terminals Notation, Figure 34 ... 26
6/11—Rev. 0 to Rev. A
Changes to Ordering Guide .. 28
1/11—Revision 0: Initial Version
Rev. C | Page 2 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide
ADXRS450 Data Sheet TABLE OF CONTENTS
Features .. 1 Mechanical Considerations for Mounting .. 10 Applications ... 1 Applications Circuits ... 10 General Description ... 1 ADXRS450 Signal Chain Timing ... 10 Functional Block Diagram .. 1 SPI Communication Protocol ... 12 Revision History ... 2 Command/Response ... 12 Specifications ... 3 SPI Communications Characteristics .. 13 Absolute Maximum Ratings .. 4 SPI Applications ... 14 Thermal Resistance .. 4 SPI Rate Data Format ... 19 Rate Sensitive Axis ... 4 Memory Map and Registers .. 20 ESD Caution .. 4 Memory Map .. 20 Pin Configuration and Function Descriptions ... 5 Memory Register Definitions ... 21 Typical Performance Characteristics ... 7 Package Orientation and Layout Information .. 23 Theory of Operation .. 9 Package Marking Codes .. 25 Continuous Self-Test .. 9 Outline Dimensions ... 26 Applications Information .. 10 Ordering Guide .. 27
REVISION HISTORY 5/13—Rev. B to Rev. C
Changes to Features Section.. 1 Changed Null Accuracy from ±3°/sec to ±6°/sec... 3 Deleted Figure 6 from Low-Pass Filter Cut-Off (−3 dB) Frequency Test Conditions/Comments and Figure 7 from ST Low-Pass Filter −3 dB Frequency Test Conditions/Comments. .. 3 Changes to Figure 6, Figure 7, and Figure 11 ... 7 Deleted Figure 10; Renumbered Sequentially... 7 Deleted Figure 13 and Figure 15 ... 8 Added Figure 12; Renumbered Sequentially .. 8 Changes to Figure 13 and Figure 15 ... 8 Deleted Calibrated Performance Section .. 10 Changes to Applications Circuits Section ... 11 Changes to Figure 25 .. 18 Changed Heading in Table 14 to 16-Bit Rate Data .. 19 Updated Outline Dimensions ... 26
12/11—Rev. A to Rev. B
Changes to the Rate Sensitive Axis Section .. 4 Changes to Figure 5 .. 6 Changes to Figure 28 .. 23 Deleted Figure 31, Renumbered Sequentially... 24 Changes to Back Side Terminals Notation, Figure 34 ... 26
6/11—Rev. 0 to Rev. A
Changes to Ordering Guide .. 28
1/11—Revision 0: Initial Version
Rev. C | Page 2 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide