Datasheet ADXL346 (Analog Devices) - 36

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Data Sheet ADXL346 NOISE PERFORMANCE 7 X-AXIS, NORMAL POWER
The specification of noise shown in Table 1 corresponds to the
6 Y-AXIS, NORMAL POWER Z-AXIS, NORMAL POWER
typical noise performance of the ADXL346 in normal power
X-AXIS, LOW POWER
operation with an output data rate of 100 Hz (LOW_POWER
5 Y-AXIS, LOW POWER B rms) Z-AXIS, LOW POWER
bit = 0, rate = 0x0A in the BW_RATE register, Address 0x2C).
S L ( 4
For normal power operation at data rates below 100 Hz, the noise
E IS
of the ADXL346 is equivalent to the noise at 100 Hz ODR in
NO 3
LSBs. For data rates greater than 100 Hz, the noise increases
UT P
approximately by a factor of √2 per doubling of the data rate.
UT 2 O
For example, at 400 Hz ODR, the noise on the x- and y-axes is
1
typically less than 2 LSB rms, and the noise on the z-axis is 147 typically less than 3 LSB rms.
0
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3.13 6.25 12.50 25 50 100 200 400 800 1600 3200
For low power operation (LOW_POWER bit = 1 in the BW_RATE
OUTPUT DATA RATE (Hz)
register, Address 0x2C), the noise of the ADXL346 is constant Figure 54. Noise vs. Output Data Rate for Normal and Low Power Modes, for all valid data rates shown in Table 8. This value is typically Full Resolution (256 LSB/g) less than 2.83 LSB rms for the x- and y-axes and typically less
10k
than 4.25 LSB rms for the z-axis.
X-AXIS Y-AXIS Z-AXIS
The trend of noise performance for both normal power and low
)
power modes of operation of the ADXL346 is shown in Figure 54.
g µ ( 1k
Figure 55 shows the typical Allan deviation for the ADXL346.
TION
The 1/f corner of the device, as shown in this figure, is very low,
IA V
allowing absolute resolution of approximately 100 µg (assuming
AN DE
that there is sufficient integration time). The figure also shows
L 100 AL
that the noise density is 420 µg/√Hz for the x- and y-axes and 530 µg/√Hz for the z-axis. 148 Figure 56 shows the typical noise performance trend of the
10
08167- ADXL346 over supply voltage. The performance is normalized
0.01 0.1 1 10 100 1k 10k
to the tested and specified supply voltage, V
AVERAGING PERIOD, (s)
S = 2.6 V. The x-axis offers the best noise performance over supply voltage, increasing by Figure 55. Allan Deviation typical y less than 25% from nominal at a supply voltage of 1.8 V.
150
The performance of the y- and z-axes is comparable, with both
) % X-AXIS (
axes increasing by typical y less than 35% when operating with a
E 140 Y-AXIS OIS
supply voltage of 1.8 V. It should be noted, as shown in Figure 54,
Z-AXIS N D
that the noise on the z-axis is typical y higher than that on the
130 LIZE
y-axis; therefore, although the noise on the z- and y-axes change
A M
roughly the same in percentage over supply voltage, the magnitude
120 OR
of change on the z-axis is greater than the magnitude of change
OF N
on the y-axis.
110 GE A T EN C 100 PER
149
90
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1.6 1.8 2.0 2.2 2.4 2.6 2.8 SUPPLY VOLTAGE, VS (V)
Figure 56. Normalized Noise vs. Supply Voltage Rev. C | Page 35 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SEQUENCING POWER SAVINGS Power Modes Autosleep Mode Standby Mode SERIAL COMMUNICATIONS SPI Preventing Bus Traffic Errors I2C INTERRUPTS DATA_READY Bit SINGLE_TAP Bit DOUBLE_TAP Bit Activity Bit Inactivity Bit FREE_FALL Bit Watermark Bit Overrun Bit Orientation Bit FIFO Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from FIFO SELF-TEST REGISTER MAP REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_TAP (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable Bits and INACT_x Enable Bits Register 0x28—THRESH_FF (Read/Write) Register 0x29—TIME_FF (Read/Write) Register 0x2A—TAP_AXES (Read/Write) Improved Tap Bit Suppress Bit TAP_x Enable Bits Register 0x2B—ACT_TAP_STATUS (Read Only) ACT_x Source and TAP_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit FULL_RES Bit Justify Bit Range Bits Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Register 0x3A—TAP_SIGN (Read Only) xSIGN Bits xTAP Bits Register 0x3B—ORIENT_CONF (Read/Write) INT_ORIENT Bit Dead Zone Bits INT_3D Bit Divisor Bits Register 0x3C—Orient (Read Only) Vx Bits xD_ORIENT Bits APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING MECHANICAL CONSIDERATIONS FOR MOUNTING TAP DETECTION IMPROVED TAP DETECTION TAP SIGN THRESHOLD LINK MODE SLEEP MODE VS. LOW POWER MODE OFFSET CALIBRATION USING SELF-TEST ORIENTATION SENSING DATA FORMATTING OF UPPER DATA RATES NOISE PERFORMANCE OPERATION AT VOLTAGES OTHER THAN 2.6 V OFFSET PERFORMANCE AT LOWEST DATA RATES AXES OF ACCELERATION SENSITIVITY LAYOUT AND DESIGN RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE