Datasheet ADXL375 (Analog Devices)

制造商Analog Devices
描述3-Axis, ±200 g Digital MEMS Accelerometer
页数 / 页33 / 1 — 3-Axis, ±200 g. Digital MEMS Accelerometer. Data Sheet. ADXL375. …
修订版B
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3-Axis, ±200 g. Digital MEMS Accelerometer. Data Sheet. ADXL375. FEATURES. GENERAL DESCRIPTION

Datasheet ADXL375 Analog Devices, 修订版: B

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3-Axis, ±200 g Digital MEMS Accelerometer Data Sheet ADXL375 FEATURES GENERAL DESCRIPTION Low power: as low as 35 µA in measurement mode and
The ADXL375 is a small, thin, 3-axis accelerometer that provides
0.1 µA in standby mode at VS = 2.5 V
low power consumption and high resolution measurement up
Power consumption scales automatically with bandwidth
to ±200 g. The digital output data is formatted as 16-bit, twos
Embedded, 32-level FIFO buffer minimizes processor load
complement data and is accessible through a SPI (3- or 4-wire)
Bandwidth of up to 1 kHz
or I2C digital interface.
Bandwidth selectable via serial command
An integrated memory management system with a 32-level first in,
Shock event detection
first out (FIFO) buffer can be used to store data to minimize host
Activity/inactivity monitoring
processor activity and lower overall system power consumption.
Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to V
Low power modes enable intelligent motion-based power
S SPI (3- or 4-wire) and I2C digital interfaces
management with threshold sensing and active acceleration
Wide temperature range: −40°C to +85°C
measurement at extremely low power dissipation.
10,000 g shock survival
The ADXL375 is supplied in a small, thin, 3 mm × 5 mm ×
Pb free/RoHS compliant
1 mm, 14-lead LGA.
Small and thin: 3 mm × 5 mm × 1 mm LGA package APPLICATIONS Concussion and head trauma detection High force event detection FUNCTIONAL BLOCK DIAGRAM VS VDD I/O ADXL375 POWER MANAGEMENT CONTROL INT1 SENSE ADC AND ELECTRONICS DIGITAL INTERRUPT 3-AXIS FILTER LOGIC INT2 SENSOR SDA/SDI/SDIO 32-LEVEL SERIAL I/O FIFO SDO/ALT ADDRESS SCL/SCLK
001
GND CS
1669- 1 Figure 1.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Soldering Profile Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Current Consumption and Output Data Rate Power Saving Modes Low Power Mode Autosleep Mode Standby Mode FIFO Buffer Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from the FIFO Buffer Self-Test Interrupts Enabling and Disabling Interrupts Clearing Interrupts Bits in the Interrupt Registers DATA_READY Bit SINGLE_SHOCK Bit DOUBLE_SHOCK Bit Activity Bit Inactivity Bit Watermark Bit Overrun Bit Serial Communications SPI Mode Preventing Bus Traffic Errors I2C Mode Register Map Register Descriptions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_SHOCK (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable and INACT_x Enable Bits Register 0x2A—SHOCK_AXES (Read/Write) Suppress Bit SHOCK_x Enable Bits Register 0x2B—ACT_SHOCK_STATUS (Read Only) ACT_x Source and SHOCK_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit Justify Bit Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Shock Detection Threshold Detection and Bandwidth Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Package Information Outline Dimensions Ordering Guide