Datasheet ADXL356, ADXL357 (Analog Devices) - 37

Data Sheet ADXL356/ADXL357 Z-AXIS OFFSET TRIM REGISTERS Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Table 38. Bit Descriptions for OFFSET_Z_H Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z, Offset added to z-axis data after all other signal processing. Data is in twos complement 0x0 R/W Bits[15:8] format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].
Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Table 39. Bit Descriptions for OFFSET_Z_L Bits Bit Name Settings Description Reset Access
[7:0] OFFSET_Z, Offset added to z-axis data after all other signal processing. Data is in twos complement 0x0 R/W Bits[7:0] format. The significance of OFFSET_Z[15:0] matches the significance of ZDATA[19:4].
ACTIVITY ENABLE REGISTER Address: 0x24, Reset: 0x00, Name: ACT_EN Table 40. Bit Descriptions for ACT_EN Bits Bit Name Settings Description Reset Access
[7:3] Reserved Reserved. 0x0 R 2 ACT_Z Z-axis data is a component of the activity detection algorithm. 0x0 R/W 1 ACT_Y Y-axis data is a component of the activity detection algorithm. 0x0 R/W 0 ACT_X X-axis data is a component of the activity detection algorithm. 0x0 R/W
ACTIVITY THRESHOLD REGISTERS Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Table 41. Bit Descriptions for ACT_THRESH_H Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH[15:8] Threshold for activity detection. Acceleration magnitude must be above 0x0 R/W ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of ACT_THRESH[15:0] matches the significance of XDATA[18:3], YDATA[18:3], and ZDATA[18:3].
Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Table 42. Bit Descriptions for THRESH_ACT_X_L Bits Bit Name Settings Description Reset Access
[7:0] ACT_THRESH[7:0] Threshold for activity detection. The acceleration magnitude must be greater 0x0 R/W than the value in ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of ACT_THRESH[15:0] matches the bit significance of XDATA[18:3], YDATA[18:3], and ZDATA[18:3].
ACTIVITY COUNT REGISTER Address: 0x27, Reset: 0x01, Name: ACT_COUNT Table 43. Bit Descriptions for ACT_COUNT Bits Bit Name Settings Description Reset Access
[7:0] ACT_COUNT Number of consecutive events above threshold (from ACT_THRESH) required to 0x1 R/W detect activity Rev. 0 | Page 37 of 42 Document Outline Features Applications Functional Block Diagrams General Description Revision History Specifications Analog Output for the ADXL356 Digital Output for the ADXL357 SPI Digital Interface Characteristics for the ADXL357 I2C Digital Interface Characteristics for the ADXL357 Absolute Maximum Ratings Thermal Resistance Recommended Soldering Profile ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Root Allan Variance (RAV) ADXL357 Characteristics Theory of Operation Applications Information Analog Output Digital Output Axes of Acceleration Sensitivity Power Sequencing Power Supply Description VSUPPLY V1P8ANA V1P8DIG VDDIO Overrange Protection Self Test Filter Serial Communications SPI Protocol I2C Protocol Reading Acceleration or Temperature Data from the Interface FIFO Interrupts DATA_RDY DRDY Pin FIFO_FULL FIFO_OVR Activity NVM_BUSY External Synchronization and Interpolation EXT_SYNC = 00—No External Sync or Interpolation EXT_SYNC = 10—External Sync with Interpolation EXT_SYNC = 01—External Sync and External Clock, No Interpolation Filter ADXL357 Register Map Register Definitions Analog Devices ID Register Address: 0x00, Reset: 0xAD, Name: DEVID_AD Analog Devices MEMS ID Register Address: 0x01, Reset: 0x1D, Name: DEVID_MST Device ID Register Address: 0x02, Reset: 0xED, Name: PARTID Product Revision ID Register Address: 0x03, Reset: 0x01, Name: REVID Status Register Address: 0x04, Reset: 0x00, Name: Status FIFO Entries Register Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES Temperature Data Registers Address: 0x06, Reset: 0x00, Name: TEMP2 Address: 0x07, Reset: 0x00, Name: TEMP1 X-Axis Data Registers Address: 0x08, Reset: 0x00, Name: XDATA3 Address: 0x09, Reset: 0x00, Name: XDATA2 Address: 0x0A, Reset: 0x00, Name: XDATA1 Y-Axis Data Registers Address: 0x0B, Reset: 0x00, Name: YDATA3 Address: 0x0C, Reset: 0x00, Name: YDATA2 Address: 0x0D, Reset: 0x00, Name: YDATA1 Z-Axis Data Registers Address: 0x0E, Reset: 0x00, Name: ZDATA3 Address: 0x0F, Reset: 0x00, Name: ZDATA2 Address: 0x10, Reset: 0x00, Name: ZDATA1 FIFO Access Register Address: 0x11, Reset: 0x00, Name: FIFO_DATA X-Axis Offset Trim Registers Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L Y-Axis Offset Trim Registers Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L Z-Axis Offset Trim Registers Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L Activity Enable Register Address: 0x24, Reset: 0x00, Name: ACT_EN Activity Threshold Registers Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L Activity Count Register Address: 0x27, Reset: 0x01, Name: ACT_COUNT Filter Settings Register Address: 0x28, Reset: 0x00, Name: Filter FIFO Samples Register Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES Interrupt Pin (INTx) Function Map Register Address: 0x2A, Reset: 0x00, Name: INT_MAP Data Synchronization Address: 0x2B, Reset: 0x00, Name: Sync I2C Speed, Interrupt Polarity, and Range Register Address: 0x2C, Reset: 0x81, Name: Range Power Control Register Address: 0x2D, Reset: 0x01, Name: POWER_CTL Self Test Register Address: 0x2E, Reset: 0x00, Name: SELF_TEST Reset Register Address: 0x2F, Reset: 0x00, Name: Reset PCB Footprint Pattern Outline Dimensions Ordering Guide