Datasheet LTC4312 (Analog Devices)
| 制造商 | Analog Devices |
| 描述 | Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers |
| 页数 / 页 | 20 / 1 — FEATURES. DESCRIPTION. 1:2 Multiplexer/Switch for 2-Wire Bus. … |
| 文件格式/大小 | PDF / 200 Kb |
| 文件语言 | 英语 |
FEATURES. DESCRIPTION. 1:2 Multiplexer/Switch for 2-Wire Bus. Bidirectional Buffer for SDA and SCL Lines
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文件文字版本
LTC4312 Pin-Selectable, 2-Channel, 2-Wire Multiplexer with Bus Buffers
FEATURES DESCRIPTION
n
1:2 Multiplexer/Switch for 2-Wire Bus
The LTC®4312 is a hot-swappable 2-channel 2-wire bus n
Bidirectional Buffer for SDA and SCL Lines
multiplexer that allows one upstream bus to connect to n
High Noise Margin with V
any combination of downstream busses or channels.
IL = 0.3•VCC
n
ENABLE Pins Connect SDA and SCL Lines
An individual enable pin controls each connection. The n
Selectable Rise Time Accelerator Current and
LTC4312 provides bidirectional buffering, keeping the up-
Activation Voltage
stream bus capacitance isolated from the downstream bus n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses capacitances. The high noise margin allows the LTC4312 n Prevents SDA and SCL Corruption During Live Board to be interoperable with I2C devices that drive a high VOL Insertion and Removal from Backplane (> 0.4V). The LTC4312 supports level translation between n Stuck Bus Disconnect and Recovery 1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable n nature of the LTC4312 allows I/O card insertion into, and Compatible with I2C, I2C Fast Mode and SMBus n removal from, a live backplane without corruption of the ±4kV Human Body Model (HBM) ESD Ruggedness n data and clock busses. 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages If both data and clock are not simultaneously high at least once in 45ms and DISCEN is high, a FAULT signal is
APPLICATIONS
generated indicating a stuck bus low condition, the input is disconnected from each enabled output channel and up n Telecommunications Systems Including ATCA to 16 clocks are generated on the enabled downstream n Address Expansion busses. A three state ACC pin enables input and output n Level Translator side rise time accelerators of varying strengths and sets n Capacitance Buffers/Bus Extender the VIL,RISING voltage. n Live Board Insertion L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n PMBus Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION
3.3V 3.3V
Rising Edge from Asserted Low with Level Translation
0.01μF 0.01μF 10k 10k VCC VCC2 10k 10k 6V CSCLOUT1 + CSCLOUT2 = 100pF SCLIN SCLIN CSCLIN = 50pF SCLOUT2 5V SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 SCLOUT1 3.3V 5V /DIV 1V 3.3V LTC4312 SCLIN 10k 10k 10k ACC SCLOUT2 SCLOUT2 DISCEN SDAOUT2 SDAOUT2 FAULT FAULT 0V GND 200ns/DIV 4312 TA01b 4314 TA01a 4312f 1
FEATURES DESCRIPTION
n
1:2 Multiplexer/Switch for 2-Wire Bus
The LTC®4312 is a hot-swappable 2-channel 2-wire bus n
Bidirectional Buffer for SDA and SCL Lines
multiplexer that allows one upstream bus to connect to n
High Noise Margin with V
any combination of downstream busses or channels.
IL = 0.3•VCC
n
ENABLE Pins Connect SDA and SCL Lines
An individual enable pin controls each connection. The n
Selectable Rise Time Accelerator Current and
LTC4312 provides bidirectional buffering, keeping the up-
Activation Voltage
stream bus capacitance isolated from the downstream bus n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses capacitances. The high noise margin allows the LTC4312 n Prevents SDA and SCL Corruption During Live Board to be interoperable with I2C devices that drive a high VOL Insertion and Removal from Backplane (> 0.4V). The LTC4312 supports level translation between n Stuck Bus Disconnect and Recovery 1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable n nature of the LTC4312 allows I/O card insertion into, and Compatible with I2C, I2C Fast Mode and SMBus n removal from, a live backplane without corruption of the ±4kV Human Body Model (HBM) ESD Ruggedness n data and clock busses. 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages If both data and clock are not simultaneously high at least once in 45ms and DISCEN is high, a FAULT signal is
APPLICATIONS
generated indicating a stuck bus low condition, the input is disconnected from each enabled output channel and up n Telecommunications Systems Including ATCA to 16 clocks are generated on the enabled downstream n Address Expansion busses. A three state ACC pin enables input and output n Level Translator side rise time accelerators of varying strengths and sets n Capacitance Buffers/Bus Extender the VIL,RISING voltage. n Live Board Insertion L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n PMBus Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION
3.3V 3.3V
Rising Edge from Asserted Low with Level Translation
0.01μF 0.01μF 10k 10k VCC VCC2 10k 10k 6V CSCLOUT1 + CSCLOUT2 = 100pF SCLIN SCLIN CSCLIN = 50pF SCLOUT2 5V SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 SCLOUT1 3.3V 5V /DIV 1V 3.3V LTC4312 SCLIN 10k 10k 10k ACC SCLOUT2 SCLOUT2 DISCEN SDAOUT2 SDAOUT2 FAULT FAULT 0V GND 200ns/DIV 4312 TA01b 4314 TA01a 4312f 1