Datasheet LTC4304 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| 页数 / 页 | 16 / 8 — OPERATION. Figure 1. Input-Output Connection tPLH. Figure 2. Input-Output … |
| 文件格式/大小 | PDF / 660 Kb |
| 文件语言 | 英语 |
OPERATION. Figure 1. Input-Output Connection tPLH. Figure 2. Input-Output Connection tPHL. READY Digital Output. FAULT
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LTC4304
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 50pF 150pF 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV 4303 F01 200ns/DIV 4303 F02 20ns/DIV
Figure 1. Input-Output Connection tPLH Figure 2. Input-Output Connection tPHL
same, a difference in rise-time occurs which is directly
READY Digital Output
proportional to the difference in capacitance between the The READY pin provides a digital fl ag which indicates the two sides. This effect is displayed in Figure 1 for a VCC status of the connection circuitry described previously in = 3.3V and a 10k pull-up resistor on each side (50pF on the “Connection Circuitry” section. READY is high when one side and 150pF on the other). Since the output side the connection circuitry is active, and pulls low when has less capacitance than the input, it rises faster and the there is not a valid connection. The pin is driven by an effective tPLH is negative. open drain pull-down capable of sinking 3mA while hold- There is a propagation delay, tPHL, through the connec- ing 0.4V on the pin. Connect a resistor of 10k to VCC to tion circuitry for falling waveforms. Figure 2 shows the provide the pull-up. falling edge waveforms. An external driver pulls down the voltage on the side with 50pF capacitance; LTC4304
FAULT Digital Output
pulls down the voltage on the opposite side with a delay The FAULT pin provides a digital fl ag which is low when of 80ns. This delay is always positive and is a function of SDAOUT and SCLOUT have not both been high within 30ms supply voltage, temperature and the pull-up resistors and (typical). The pin is driven by an open drain pull-down equivalent bus capacitances on both sides of the bus. The capable of sinking 3mA while holding 0.4V on the pin. Typical Performance Characteristics section shows tPHL Connect a resistor of 10k to VCC to provide the pull-up. as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides
ENABLE
of the part. Larger output capacitances translate to longer When the ENABLE pin is driven below 0.8V with respect delays. Users must quantify the difference in propagation to the LTC4304’s ground, the backplane side is discon- times for a rising edge versus a falling edge in their systems nected from the card side, and the READY pin is internally and adjust setup and hold times accordingly. pulled low. When the pin is driven above 2V, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before connecting the two sides. At this time the internal pulldown on READY releases. When ENABLE is low, automatic clocking is disabled. 4304fa 8
OPERATION
OUTPUT SIDE INPUT SIDE INPUT SIDE OUTPUT SIDE 50pF 150pF 50pF 150pF 0.5V/DIV 0.5V/DIV 0.5V/DIV 0.5V/DIV 4303 F01 200ns/DIV 4303 F02 20ns/DIV
Figure 1. Input-Output Connection tPLH Figure 2. Input-Output Connection tPHL
same, a difference in rise-time occurs which is directly
READY Digital Output
proportional to the difference in capacitance between the The READY pin provides a digital fl ag which indicates the two sides. This effect is displayed in Figure 1 for a VCC status of the connection circuitry described previously in = 3.3V and a 10k pull-up resistor on each side (50pF on the “Connection Circuitry” section. READY is high when one side and 150pF on the other). Since the output side the connection circuitry is active, and pulls low when has less capacitance than the input, it rises faster and the there is not a valid connection. The pin is driven by an effective tPLH is negative. open drain pull-down capable of sinking 3mA while hold- There is a propagation delay, tPHL, through the connec- ing 0.4V on the pin. Connect a resistor of 10k to VCC to tion circuitry for falling waveforms. Figure 2 shows the provide the pull-up. falling edge waveforms. An external driver pulls down the voltage on the side with 50pF capacitance; LTC4304
FAULT Digital Output
pulls down the voltage on the opposite side with a delay The FAULT pin provides a digital fl ag which is low when of 80ns. This delay is always positive and is a function of SDAOUT and SCLOUT have not both been high within 30ms supply voltage, temperature and the pull-up resistors and (typical). The pin is driven by an open drain pull-down equivalent bus capacitances on both sides of the bus. The capable of sinking 3mA while holding 0.4V on the pin. Typical Performance Characteristics section shows tPHL Connect a resistor of 10k to VCC to provide the pull-up. as a function of temperature and voltage for 10k pull-up resistors and 100pF equivalent capacitance on both sides
ENABLE
of the part. Larger output capacitances translate to longer When the ENABLE pin is driven below 0.8V with respect delays. Users must quantify the difference in propagation to the LTC4304’s ground, the backplane side is discon- times for a rising edge versus a falling edge in their systems nected from the card side, and the READY pin is internally and adjust setup and hold times accordingly. pulled low. When the pin is driven above 2V, the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before connecting the two sides. At this time the internal pulldown on READY releases. When ENABLE is low, automatic clocking is disabled. 4304fa 8