Datasheet MCP47DA1 (Microchip) - 4

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MCP47DA1 AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to +5.5V. CL = 1 nF, RL = 5 k . Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Supply Voltage VDD 2.7 — 5.5 V Analog Characteristics specified 1.8 — 5.5 V Digital Characteristics specified VDD Start Voltage VBOR — — 1.65 V RAM retention voltage (VRAM) < VBOR to ensure wiper to default Reset state VDD Rise Rate to VDDRR
Note 5
V/ms ensure Power-on Reset Delay after device TBORD — — 1 µS exits the Reset state (VDD > VBOR) to Digital Interface Active Delay after device TOUTV 20 µS Within ± 0.5 LSb of VREF/2 exits the Reset (for default POR/BOR wiper value). state (VDD > VBOR) to VOUT valid Supply Current IDD — 130 200 µA Serial Interface Active,
(Note 6)
Write all 0’s to volatile wiper, No Load on VOUT VDD = 5.5V, VREF = 1.5V, FSCL = 400 kHz — 100 160 µA Serial Interface Inactive (Static), (Stop condition, SCL = SDA = VIH), No Load on VOUT Wiper = 0, VDD = 5.5V, VREF = 1.5V VREF Input Range VRE F 1 — VDD V For VDD  3.0V VREF  VDD For VDD < 3.0V VREF  (VDD - 1.0V)/(2/3) (
Note 7
)
Note 1:
Resistance is defined as the resistance between the VREF pin and the VSS pin.
2:
INL and DNL are measured at VOUT from Code = 20h (Zero Scale) through Code = 60h (Full Scale).
3:
This specification by design.
4:
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature.
5:
POR/BOR is not rate dependent.
6:
Supply current is independent of VREF current.
7:
See
Section 7.1.3
. DS25118D-page 4  2012-2013 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 I2C Mode Timing Waveforms and Requirements FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms. FIGURE 1-2: I2C Bus Data Timing. TABLE 1-1: I2C Bus Start/Stop Bits Requirements TABLE 1-2: I2C Bus Data Requirements (Slave Mode) 2.0 Typical Performance Curves FIGURE 2-1: INL vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V. FIGURE 2-2: INL vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V. FIGURE 2-3: INL vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V. FIGURE 2-4: INL vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V. FIGURE 2-5: INL vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V. FIGURE 2-6: INL vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V. FIGURE 2-7: INL vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V. FIGURE 2-8: INL vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V. FIGURE 2-9: INL vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V. FIGURE 2-10: INL vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V. FIGURE 2-11: INL vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V. FIGURE 2-12: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V FIGURE 2-13: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V FIGURE 2-14: DNL vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V FIGURE 2-15: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V FIGURE 2-16: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V FIGURE 2-17: DNL vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V FIGURE 2-18: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V FIGURE 2-19: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V FIGURE 2-20: DNL vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V FIGURE 2-21: DNL vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V FIGURE 2-22: DNL vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V FIGURE 2-23: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V. FIGURE 2-24: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 1.65V. FIGURE 2-25: Full-Scale Error (FSE) vs. Temperature. VDD = 5.5V, VREF = 1.0V. FIGURE 2-26: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 3.6V. FIGURE 2-27: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 1.65V. FIGURE 2-28: Full-Scale Error (FSE) vs. Temperature. VDD = 3.6V, VREF = 1.0V FIGURE 2-29: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 3.0V FIGURE 2-30: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 1.65V. FIGURE 2-31: Full-Scale Error (FSE) vs. Temperature. VDD = 3.0V, VREF = 1.0V FIGURE 2-32: Full-Scale Error (FSE) vs. Temperature. VDD = 2.7V, VREF = 1.65V. FIGURE 2-33: Full-Scale Error (FSE) vs. Temperature. VDD = 2.7V, VREF = 1.0V FIGURE 2-34: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 5.5V FIGURE 2-35: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 1.65V FIGURE 2-36: Zero-Scale Error (ZSE) vs. Temperature. VDD = 5.5V, VREF = 1.0V FIGURE 2-37: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 3.6V FIGURE 2-38: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 1.65V FIGURE 2-39: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.6V, VREF = 1.0V FIGURE 2-40: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 3.0V FIGURE 2-41: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 1.65V FIGURE 2-42: Zero-Scale Error (ZSE) vs. Temperature. VDD = 3.0V, VREF = 1.0V FIGURE 2-43: Zero-Scale Error (ZSE) vs. Temperature. VDD = 2.7V, VREF = 1.65V FIGURE 2-44: Zero-Scale Error (ZSE) vs. Temperature. VDD = 2.7V, VREF = 1.0V FIGURE 2-45: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 5.5V. FIGURE 2-46: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 1.65V. FIGURE 2-47: Total Unadjusted Error vs. Code and Temperature. VDD = 5.5V, VREF = 1.0V. FIGURE 2-48: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 3.6V. FIGURE 2-49: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 1.65V. FIGURE 2-50: Total Unadjusted Error vs. Code and Temperature. VDD = 3.6V, VREF = 1.0V. FIGURE 2-51: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 3.0V. FIGURE 2-52: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 1.65V. FIGURE 2-53: Total Unadjusted Error vs. Code and Temperature. VDD = 3.0V, VREF = 1.0V. FIGURE 2-54: Total Unadjusted Error vs. Code and Temperature. VDD = 2.7V, VREF = 1.65V. FIGURE 2-55: Total Unadjusted Error vs. Code and Temperature. VDD = 2.7V, VREF = 1.0V. FIGURE 2-56: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 5.5V. FIGURE 2-57: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 1.65V. FIGURE 2-58: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 5.5V, VREF = 1.0V. FIGURE 2-59: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 3.6V. FIGURE 2-60: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 1.65V. FIGURE 2-61: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.6V, VREF = 1.0V. FIGURE 2-62: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 3.0V. FIGURE 2-63: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 1.65V. FIGURE 2-64: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 3.0V, VREF = 1.0V. FIGURE 2-65: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 2.7V, VREF = 1.65V. FIGURE 2-66: VOUT Tempco vs. Code ( (VOUT(+125C) - VOUT(-40C) / VOUT(+25C,Code=FS) / 165 ) * 1,000,000 ), VDD = 2.7V, VREF = 1.0V. FIGURE 2-67: INL vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. FIGURE 2-68: INL vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. FIGURE 2-69: INL vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 5.5V, Temp = +25°C. FIGURE 2-70: INL vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. FIGURE 2-71: DNL vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. FIGURE 2-72: DNL vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. FIGURE 2-73: DNL vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 3.0V, Temp = +25°C. FIGURE 2-74: DNL vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. FIGURE 2-75: Total Unadjusted Error vs. Code and VREF. VDD = 5.5V, VREF = 1V, 1.65V, 2.7V, and 5.5V, Temp = +25°C. FIGURE 2-76: Total Unadjusted Error vs. Code and VREF. VDD = 3.6V, VREF = 1V, 1.65V, and 3.6V, Temp = +25°C. FIGURE 2-77: Total Unadjusted Error vs. Code and VREF. VDD = 3.0V, VREF = 1V, 1.65V, and 5.5V, Temp = +25°C. FIGURE 2-78: Total Unadjusted Error vs. Code and VREF. VDD = 2.7V, VREF = 1V, 1.65V, and 2.55V, Temp = +25°C. FIGURE 2-79: VIH / VIL Threshold of SDA/SCL Inputs vs. Temperature and VDD. FIGURE 2-80: VOL (SDA) vs. VDD and Temperature. FIGURE 2-81: VOUT vs. VDD and Temperature. For VDD Power-Up and Power- Down with VREF = 1.5V. FIGURE 2-82: Interface Active Current (IDD) vs. SCL Frequency (fSCL) and Temperature VDD = 2.7V and 5.5V, VREF = 1.5V and VDD. (no load on VOUT). FIGURE 2-83: Interface Inactive Current (ISHDN) vs. Temperature. VDD = 2.7V and 5.5V, VREF = 1.5V and VDD. (no load on VOUT, SCL = SDA = VDD). FIGURE 2-84: VOUT vs. Source/Sink Current. VDD = 5.0V. FIGURE 2-85: VOUT vs. Resistive Load. VDD = 5.0V. FIGURE 2-86: VOUT Accuracy vs. VDD and Temperature. FIGURE 2-87: VOUT vs. Source/Sink Current. VDD = 3.0V. FIGURE 2-88: VOUT vs. Resistive Load. VDD = 3.0V. FIGURE 2-89: RVREF Resistances vs. VDD and Temperature. FIGURE 2-90: Zero-Scale to Full-Scale Settling Time (20h to 60h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 1nF. FIGURE 2-91: Full-Scale to Zero-Scale Settling Time (60h to 20h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 1nF. FIGURE 2-92: Half-Scale Settling Time (30h to 50h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 1nF. FIGURE 2-93: Half-Scale Settling Time (50h to 30h), VDD = 5.0V, VREF = 5.0V, RL = 5kW, CL = 1nF. FIGURE 2-94: Digital Feedthrough (SCL signal coupling to VOUT pin); VOUT = 40h, FSCL = 100kHz, VDD = 5.0V, VREF = 5.0V. 3.0 Pin Descriptions TABLE 3-1: Pinout Description for The MCP47DA1 3.1 Positive Power Supply Input (VDD) 3.2 Ground (VSS) 3.3 I2C Serial Clock (SCL) 3.4 I2C Serial Data (SDA) 3.5 Analog Output Voltage Pin (VOUT) 3.6 Voltage Reference Pin (VREF) 4.0 General Overview FIGURE 4-1: Resistor Network and Output Buffer Block Diagram. 4.1 POR/BOR Operation TABLE 4-1: Default POR Wiper Setting Selection TABLE 4-2: Device functionality at each VDD Region (Note 1) FIGURE 4-2: Power-up and Brown-out. 5.0 Serial Interface – I2C Module FIGURE 5-1: Typical Application I2C Bus Configurations. 5.1 I2C I/O Considerations 5.2 I2C Bit Definitions FIGURE 5-2: Start Bit. FIGURE 5-3: Data Bit. FIGURE 5-4: Acknowledge Waveform. TABLE 5-1: MCP47DA1 A/A Responses FIGURE 5-5: Repeat Start Condition Waveform. FIGURE 5-6: Stop Condition Receive or Transmit Mode. FIGURE 5-7: Typical 16-bit I2C Waveform Format. FIGURE 5-8: I2C Data States and Bit Sequence. FIGURE 5-9: Slave Address Bits in the I2C Control Byte. TABLE 5-2: Device I2C Address FIGURE 5-10: General Call Formats. 5.3 Serial Commands FIGURE 5-11: I2C Single Byte Write Command Format. FIGURE 5-12: I2C Write Command Format. FIGURE 5-13: I2C Write Communication Behavior. FIGURE 5-14: I2C Read Command Format. FIGURE 5-15: I2C Read Communication Behavior. 6.0 Resistor Network 6.1 RVREF Resistance 6.2 R1 and R2 Fixed Resistors 6.3 RAB Resistor Ladder FIGURE 6-1: Resistor Network and Output Buffer Block Diagram. 6.4 Serial Buffer to Wiper Register Decode TABLE 6-1: Serial Shift Register value to Wiper Value 6.5 Resistor Variations (Voltage and Temperature) 6.6 POR Value TABLE 6-2: POR/BOR Settings 7.0 Output Buffer 7.1 Output Buffer/VOUT Operation FIGURE 7-1: Output Buffer Block Diagram. TABLE 7-1: Theoretical DAC Output Values (Wiper Value = I2C Write Data - 20h) TABLE 7-2: VREF ¹ VDD and Full-Scale Output TABLE 7-3: VREF = VDD and Not Full-Scale Output FIGURE 7-2: Solving for VOUT, VREF, or DAC Register Code. 7.2 Output Slew Rate FIGURE 7-3: VOUT pin Slew Rate. 7.3 Driving Resistive and Capacitive Loads FIGURE 7-4: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). 7.4 Output Errors TABLE 7-4: Calculation Comparison FIGURE 7-5: Output Voltage (VOUT) Error. 8.0 Applications Examples 8.1 DC Set Point or Calibration FIGURE 8-1: Set Point or Threshold Calibration. FIGURE 8-2: Example Circuit Of Set Point or Threshold Calibration. FIGURE 8-3: Single-Supply “Window” DAC. 8.2 Selectable Gain and Offset Bipolar Voltage Output FIGURE 8-4: Bipolar Voltage Source with Selectable Gain and Offset Circuit. FIGURE 8-5: Simplified Bipolar Voltage Source with Selectable Gain and Offset Circuit. 8.3 Building Programmable Current Source FIGURE 8-6: Digitally-Controlled Current Source. 8.4 Serial Interface Communication Times TABLE 8-1: Serial Interface Times / Frequencies 8.5 Software I2C Interface Reset Sequence FIGURE 8-7: Software Reset Sequence Format. 8.6 Design Considerations FIGURE 8-8: Typical Microcontroller Connections. FIGURE 8-9: Example MCP47DA1 Circuit. TABLE 8-2: Package Footprint (1) FIGURE 8-10: I2C Bus Connection Test. 9.0 Development support 9.1 Evaluation/Demonstration Boards FIGURE 9-1: SC70EV Bond Out PCB – Top Layer and Silk-Screen. 9.2 Technical Documentation TABLE 9-1: Technical Documentation 10.0 Packaging Information 10.1 Package Marking Information Appendix A: Revision History Appendix B: Terminology Product ID System Trademarks Worldwide Sales