Datasheet Summary SAM D21EL, SAM D21GL (Microchip) - 2

制造商Microchip
描述32-bit ARM-Based Microcontrollers
页数 / 页38 / 2 — 32-bit ARM-Based Microcontrollers. Datasheet Summary
修订版02-01-2017
文件格式/大小PDF / 851 Kb
文件语言英语

32-bit ARM-Based Microcontrollers. Datasheet Summary

32-bit ARM-Based Microcontrollers Datasheet Summary

该数据表的模型线

ATSAMD21E15
ATSAMD21E15L
ATSAMD21E16
ATSAMD21E16L
ATSAMD21E17
ATSAMD21E18
ATSAMD21G15
ATSAMD21G16
ATSAMD21G16L
ATSAMD21G17
ATSAMD21G18
ATSAMD21J15
ATSAMD21J16
ATSAMD21J17
ATSAMD21J18

文件文字版本

32-bit ARM-Based Microcontrollers
• Up to four compare channels with optional complementary output • Generation of synchronized pulse width modulation (PWM) pattern across port pins • Deterministic fault protection, fast decay and configurable dead-time between complementary output • Dithering that increase resolution with up to 5 bit and reduce quantization error – 32-bit Real Time Counter (RTC) with clock/calendar function – Watchdog Timer (WDT) – CRC-32 generator – Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either: • USART with full-duplex and single-wire half-duplex configuration • I2C up to 3.4MHz • SPI • LIN slave – One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 18 channels • Differential and single-ended input • 1/2x to 16x programmable gain stage • Automatic offset and gain error compensation • Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution – 10-bit, 350ksps Digital-to-Analog Converter (DAC) – Four Analog Comparators (AC) with window compare function • I/O – Up to 38 programmable I/O pins • Packages – 48-pin TQFP, QFN – 32-pin QFN • Operating Voltage – 1.62V – 3.63V © 2017 Microchip Technology Inc.
Datasheet Summary
40001885A-page 2 Document Outline Introduction Features Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 3.1. SAM D21ExL 3.2. SAM D21GxL 3.3. Device Identification 4. Block Diagram 5. Pinout 5.1. SAM D21GxL 5.1.1. QFN48 5.2. SAM D21ExL 5.2.1. QFN32 / TQFP32 6. Product Mapping 7. Processor And Architecture 7.1. Cortex M0+ Processor 7.1.1. Cortex M0+ Configuration 7.1.2. Cortex-M0+ Peripherals 7.1.3. Cortex-M0+ Address Map 7.1.4. I/O Interface 7.1.4.1. Overview 7.1.4.2. Description 7.2. Nested Vector Interrupt Controller 7.2.1. Overview 7.2.2. Interrupt Line Mapping 7.3. Micro Trace Buffer 7.3.1. Features 7.3.2. Overview 7.4. High-Speed Bus System 7.4.1. Features 7.4.2. Configuration 7.4.3. SRAM Quality of Service 7.5. AHB-APB Bridge 7.6. PAC - Peripheral Access Controller 7.6.1. Overview 7.6.2. Register Description 7.6.2.1. PAC0 Register Description 7.6.2.1.1. Write Protect Clear 7.6.2.1.2. Write Protect Set 7.6.2.2. PAC1 Register Description 7.6.2.2.1. Write Protect Clear 7.6.2.2.2. Write Protect Set 7.6.2.3. PAC2 Register Description 7.6.2.3.1. Write Protect Clear 7.6.2.3.2. Write Protect Set 8. Packaging Information 8.1. Thermal Considerations 8.1.1. Thermal Resistance Data 8.1.2. Junction Temperature 8.2. Package Drawings 8.2.1. 48 pin QFN 8.2.2. 32 pin TQFP 8.2.3. 32 pin QFN 8.3. Soldering Profile The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service