Datasheet TC74HC279AP, TC74HC279AF (Toshiba)
| 制造商 | Toshiba |
| 描述 | High speed CMOS Quad S-R Latch |
| 页数 / 页 | 8 / 1 — TC74HC279AP, TC74HC279AF. Features. Pin Assignment |
| 文件格式/大小 | PDF / 277 Kb |
| 文件语言 | 英语 |
TC74HC279AP, TC74HC279AF. Features. Pin Assignment
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TC74HC279AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74HC279AP, TC74HC279AF
Quad S -R Latch The TC74HC279A is a high speed CMOS QUAD S-R LATCH fabricated with silicon gate C2MOS technology. TC74HC279AP It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Each latch has an independent Q output and Set and Reset inputs. S and R are active low. When S input is low, the Q output goes high and when R input is low, the Q output goes low. When both S and R are low, S takes precedence resulting Q = low. When both of S and R are held high, Q output doesn’t change. All inputs are equipped with protection circuits against static TC74HC279AF discharge or transient excess voltage.
Features
• High speed: tpd = 12 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL Weight • Wide operating voltage range: VCC (opr) = 2 to 6 V DIP16-P-300-2.54A : 1.00 g (typ.) • Pin and function compatible with 74LS279 SOP16-P-300-1.27A : 0.18 g (typ.)
Pin Assignment
Start of commercial production 1988-05 1 2014-03-01 Document Outline TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Features Pin Assignment IEC Logic Symbol Truth Table System Diagram Absolute Maximum Ratings (Note 1) Operating Ranges (Note) Electrical Characteristics DC Characteristics AC Characteristics (CL ( 15 pF, VCC ( 5 V, Ta ( 25°C, input: tr ( tf ( 6 ns) AC Characteristics (CL ( 50 pF, input: tr ( tf ( 6 ns) Package Dimensions Package Dimensions RESTRICTIONS ON PRODUCT USE
TC74HC279AP, TC74HC279AF
Quad S -R Latch The TC74HC279A is a high speed CMOS QUAD S-R LATCH fabricated with silicon gate C2MOS technology. TC74HC279AP It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Each latch has an independent Q output and Set and Reset inputs. S and R are active low. When S input is low, the Q output goes high and when R input is low, the Q output goes low. When both S and R are low, S takes precedence resulting Q = low. When both of S and R are held high, Q output doesn’t change. All inputs are equipped with protection circuits against static TC74HC279AF discharge or transient excess voltage.
Features
• High speed: tpd = 12 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL Weight • Wide operating voltage range: VCC (opr) = 2 to 6 V DIP16-P-300-2.54A : 1.00 g (typ.) • Pin and function compatible with 74LS279 SOP16-P-300-1.27A : 0.18 g (typ.)
Pin Assignment
Start of commercial production 1988-05 1 2014-03-01 Document Outline TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic Features Pin Assignment IEC Logic Symbol Truth Table System Diagram Absolute Maximum Ratings (Note 1) Operating Ranges (Note) Electrical Characteristics DC Characteristics AC Characteristics (CL ( 15 pF, VCC ( 5 V, Ta ( 25°C, input: tr ( tf ( 6 ns) AC Characteristics (CL ( 50 pF, input: tr ( tf ( 6 ns) Package Dimensions Package Dimensions RESTRICTIONS ON PRODUCT USE