Datasheet LTC2323-12 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Dual, 12-Bit + Sign, 5Msps Differential Input ADC with Wide Input Common Mode Range |
| 页数 / 页 | 26 / 8 — PIN FUNCTIONS VDD (Pins 1, 8):. SDO1+, SDO1– (Pins 15, 16):. IN2+, AIN2– … |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
PIN FUNCTIONS VDD (Pins 1, 8):. SDO1+, SDO1– (Pins 15, 16):. IN2+, AIN2– (Pins 2, 3):. GND (Pins 4, 5, 10, 29):
该数据表的模型线
文件文字版本
link to page 26 LTC2323-12
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data a 10µF ceramic and a 0.1µF ceramic close to the part. The Output. The conversion result is shifted MSB first on each VDD pins should be shorted together and driven from the falling edge of SCK. In CMOS mode, the result is output same supply. on SDO1+. The logic level is determined by OVDD. Do
A
not connect SDO1–. In LVDS mode, the result is output
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (A differentially on SDO1+ and SDO1–. These pins must be IN2+ – AIN2–) is ±REFOUT2 voltage. These pins can be driven from V differentially terminated by an external 100Ω resistor at DD to GND. the receiver (FPGA).
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed pad (Pin 29) must be tied directly to a solid ground plane.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. the SDO output at the receiver. In CMOS mode, the skew- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. matched clock is output on CLKOUT+. The logic level is These pins can be driven from VDD to GND. determined by OVDD. Do not connect CLKOUT–. For low
CNV (Pin 9):
Conversion Start Input. A fal ing edge on throughput applications using SCK to latch the SDO out- CNV puts the internal sample-and-hold into the hold mode put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. and starts a conversion cycle. CNV must be driven by a In LVDS mode, the skew-matched clock is output differ- low jitter clock as shown in the Typical Application on entially on CLKOUT+ and CLKOUT–. These pins must be the back page. The CNV pin is unaffected by the CMOS/ differentially terminated by an external 100Ω resistor at LVDS pin. the receiver (FPGA).
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return.
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 Output. The conversion result is shifted MSB first on each pin to the ground plane. falling edge of SCK. In CMOS mode, the result is output on SDO2+. The logic level is determined by OV
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard DD. Do not connect SDO2–. In LVDS mode, the result is output buffer nominally outputs 4.096V to this pin. This pin is differentially on SDO2+ and SDO2–. These pins must be referred to REFRTN1 and should be decoupled closely to differentially terminated by an external 100Ω resistor at the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor the receiver (FPGA). and a 10μF (X5R, 0805 size) ceramic capacitor in paral- lel. The internal buffer driving this pin may be disabled
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The by grounding the REFINT pin. If the buffer is disabled, falling edge of this clock shifts the conversion result MSB an external reference may drive this pin in the range of first onto the SDO pins. In CMOS mode, drive SCK+ with 1.25V to 5V. a single-ended clock. The logic level is determined by OVDD. Do not connect SCK–. In LVDS mode, drive SCK+
VBYP1 (Pin 13):
Bypass this internally supplied pin to and SCK–. with a differential clock. These pins must be ground with a 1µF ceramic capacitor. The nominal output differentially terminated by an external 100Ω resistor at voltage on this pin is 1.6V. the receiver (ADC).
OVDD (Pin 14):
I/O Interface Digital Power. The range of
OGND (Pin 23):
I/O Ground. This ground must be tied to OVDD is 1.71V to 2.5V. This supply is nominally set to the ground plane at a single point. OVDD is bypassed to the same supply as the host interface (CMOS: 1.8V or this pin. 2.5V, LVDS: 2.5V). Bypass OVDD to OGND with a 0.1μF capacitor. 232312fb 8 For more information www.linear.com/LTC2323-12 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts
PIN FUNCTIONS VDD (Pins 1, 8):
Power Supply. Bypass VDD to GND with
SDO1+, SDO1– (Pins 15, 16):
Channel 1 Serial Data a 10µF ceramic and a 0.1µF ceramic close to the part. The Output. The conversion result is shifted MSB first on each VDD pins should be shorted together and driven from the falling edge of SCK. In CMOS mode, the result is output same supply. on SDO1+. The logic level is determined by OVDD. Do
A
not connect SDO1–. In LVDS mode, the result is output
IN2+, AIN2– (Pins 2, 3):
Analog Differential Input Pins. Full-scale range (A differentially on SDO1+ and SDO1–. These pins must be IN2+ – AIN2–) is ±REFOUT2 voltage. These pins can be driven from V differentially terminated by an external 100Ω resistor at DD to GND. the receiver (FPGA).
GND (Pins 4, 5, 10, 29):
Ground. These pins and exposed pad (Pin 29) must be tied directly to a solid ground plane.
CLKOUT+, CLKOUT– (Pins 17, 18):
Serial Data Clock Output. CLKOUT provides a skew-matched clock to latch
AIN1–, AIN1+ (Pins 6, 7):
Analog Differential Input Pins. the SDO output at the receiver. In CMOS mode, the skew- Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage. matched clock is output on CLKOUT+. The logic level is These pins can be driven from VDD to GND. determined by OVDD. Do not connect CLKOUT–. For low
CNV (Pin 9):
Conversion Start Input. A fal ing edge on throughput applications using SCK to latch the SDO out- CNV puts the internal sample-and-hold into the hold mode put, CLKOUT+ can be disabled by tying CLKOUT– to OVDD. and starts a conversion cycle. CNV must be driven by a In LVDS mode, the skew-matched clock is output differ- low jitter clock as shown in the Typical Application on entially on CLKOUT+ and CLKOUT–. These pins must be the back page. The CNV pin is unaffected by the CMOS/ differentially terminated by an external 100Ω resistor at LVDS pin. the receiver (FPGA).
REFRTN1 (Pin 11):
Reference Buffer 1 Output Return.
SDO2+, SDO2– (Pins 19, 20):
Channel 2 Serial Data Bypass REFRTN1 to REFOUT1. Do not tie the REFRTN1 Output. The conversion result is shifted MSB first on each pin to the ground plane. falling edge of SCK. In CMOS mode, the result is output on SDO2+. The logic level is determined by OV
REFOUT1 (Pin 12):
Reference Buffer 1 Output. An onboard DD. Do not connect SDO2–. In LVDS mode, the result is output buffer nominally outputs 4.096V to this pin. This pin is differentially on SDO2+ and SDO2–. These pins must be referred to REFRTN1 and should be decoupled closely to differentially terminated by an external 100Ω resistor at the pin (no vias) with a 0.1µF (X7R, 0402 size) capacitor the receiver (FPGA). and a 10μF (X5R, 0805 size) ceramic capacitor in paral- lel. The internal buffer driving this pin may be disabled
SCK+, SCK– (Pins 21, 22):
Serial Data Clock Input. The by grounding the REFINT pin. If the buffer is disabled, falling edge of this clock shifts the conversion result MSB an external reference may drive this pin in the range of first onto the SDO pins. In CMOS mode, drive SCK+ with 1.25V to 5V. a single-ended clock. The logic level is determined by OVDD. Do not connect SCK–. In LVDS mode, drive SCK+
VBYP1 (Pin 13):
Bypass this internally supplied pin to and SCK–. with a differential clock. These pins must be ground with a 1µF ceramic capacitor. The nominal output differentially terminated by an external 100Ω resistor at voltage on this pin is 1.6V. the receiver (ADC).
OVDD (Pin 14):
I/O Interface Digital Power. The range of
OGND (Pin 23):
I/O Ground. This ground must be tied to OVDD is 1.71V to 2.5V. This supply is nominally set to the ground plane at a single point. OVDD is bypassed to the same supply as the host interface (CMOS: 1.8V or this pin. 2.5V, LVDS: 2.5V). Bypass OVDD to OGND with a 0.1μF capacitor. 232312fb 8 For more information www.linear.com/LTC2323-12 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Revision History Typical Application Related Parts