Datasheet AD5381 (Analog Devices) - 2

制造商Analog Devices
描述40-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC
页数 / 页41 / 2 — AD5381* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. …
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AD5381* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017. COMPARABLE PARTS. DESIGN RESOURCES. DOCUMENTATION

AD5381* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES DOCUMENTATION

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AD5381* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS DESIGN RESOURCES
View a parametric search of comparable parts. • AD5381 Material Declaration • PCN-PDN Information
DOCUMENTATION
• Quality And Reliability
Application Notes
• Symbols and Footprints • AN-1224: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using the
DISCUSSIONS
AD5381 DAC View all AD5381 EngineerZone Discussions. • AN-1227: AD5381 Channel Monitor Function
Data Sheet SAMPLE AND BUY
• AD5381: 40-Channel, 3 V/5 V, Single-Supply, 12-Bit, Visit the product page to see pricing options. denseDAC Data Sheet
Product Highlight TECHNICAL SUPPORT
• Extending the denseDAC™ Multichannel D/As Submit a technical question or find your regional support number.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD5380 IIO Multi-Channel DAC Linux Driver
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
REFERENCE MATERIALS Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Technical Articles
• Software Calibration Reduces D/A Converter Offset and Gain Errors
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Document Outline Features Integrated Functions Applications Functional Block Diagram Table Of Contents Revision History General Description Specifications AD5381-5 Specifications AD5381-3 Specifications AC Characteristics Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Control Register Contents Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5381 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pin A5 to Pin A0 Pin DB11 to Pin DB0 Microprocessor Interfacing Parallel Interface AD5381 to MC68HC11 AD5381 to PIC16C6x/7x AD5381 to 8051 AD5381 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing FIFO Outline Dimensions Ordering Guide