Datasheet AD7853, AD7853L (Analog Devices) - 4

AD7853/AD7853L (AVDD = DVDD = +3.0 V to +5.5 V; fCLKIN = 4 MHz for AD7853 and 1.8/1 MHz for AD7853L; TA = TMIN to TIMING SPECIFICATIONS1 TMAX, unless otherwise noted) Limit at TMIN, TMAX (A, B Versions) Parameter 5 V 3 V Units Description
f 2 CLKIN 500 500 kHz min Master Clock Frequency 4 4 MHz max 1.8 1.8 MHz max L Version, 0°C to +70°C, B Grade Only 1 1 MHz max L Version, –40°C to +85°C f 3 SCLK 4 4 MHz max Interface Modes 1, 2, 3 (External Serial Clock) fCLKIN fCLKIN MHz max Interface Modes 4, 5 (Internal Serial Clock) t 4 1 100 100 ns min CONVST Pulsewidth t2 50 90 ns max CONVST↓ to BUSY↑ Propagation Delay tCONVERT 4.6 4.6 µs max Conversion Time = 18 tCLKIN 10 (18) 10 (18) µs max L Version 1.8 (1) MHz CLKIN. Conversion Time = 18 tCLKIN t3 –0.4 tSCLK –0.4 tSCLK ns min SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input) ⫿0.4 t ⫿ SCLK 0.4 tSCLK ns min/max SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input) t4 0.6 tSCLK 0.6 tSCLK ns min SYNC↓ to SCLK↓ Setup Time. Interface Mode 4 Only t 5 5 50 90 ns max Delay from SYNC↓ until DOUT 3-State Disabled t 5 5A 50 90 ns max Delay from SYNC↓ until DIN 3-State Disabled t 5 6 75 115 ns max Data Access Time After SCLK↓ t7 40 60 ns min Data Setup Time Prior to SCLK↑ t8 20 30 ns min Data Valid to SCLK Hold Time t 6 9 0.4 tSCLK 0.4 tSCLK ns min SCLK High Pulsewidth (Interface Modes 4 and 5) t 6 10 0.4 tSCLK 0.4 tSCLK ns min SCLK Low Pulsewidth (Interface Modes 4 and 5) t11 30 50 ns min SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 30/0.4 tSCLK 50/0.4 tSCLK ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 t11A 50 50 ns max SCLK↑ to SYNC↑ Hold Time t 7 12 50 50 ns max Delay from SYNC↑ until DOUT 3-State Enabled t13 90 130 ns max Delay from SCLK↑ to DIN Being Configured as Output t 8 14 50 90 ns max Delay from SCLK↑ to DIN Being Configured as Input t15 2.5 tCLKIN 2.5 tCLKIN ns max CAL↑ to BUSY↑ Delay t16 2.5 tCLKIN 2.5 tCLKIN ns max CONVST↓ to BUSY↑ Delay in Calibration Sequence t 9 CAL 31.25 31.25 ms typ Full Self-Calibration Time, Master Clock Dependent (125013 tCLKIN) t 9 CAL1 27.78 27.78 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock Dependent (111114 tCLKIN) t 9 CAL2 3.47 3.47 ms typ System Offset Calibration Time, Master Clock Dependent (13899 tCLKIN) NOTES Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of SCLK will apply. 1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Table X and timing diagrams for different interface modes and calibration. 2Mark/Space ratio for the master clock input is 40/60 to 60/40. 3For Interface Modes 1, 2, 3 the SCLK max frequency will be 4 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f CLKIN. 4The CONVST pulsewidth will apply here only for normal operation. When the part is in power-down mode, a different CONVST pulsewidth will apply (see Power- Down section). 5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN. 7t12 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relin- quish time of the part and is independent of the bus loading. 8t14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will not occur. 9The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to the 1.8/1 MHz master clock. Specifications subject to change without notice. –4– REV. B