Datasheet AD9240 (Analog Devices) - 23

AD9240 VINA2 VINB2 D1 1N5711 D3 1N5711 D2 1N5711 D4 1N5711 +5VA A +5VA A
V V
8 R12 33 AC COUPLE OPTION J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 R15 33 R39 13 11 9 7J 5 3 1 33 27 25 23 21 19 17 15 A A F TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP3 TP4 TP5 TP17 TP6 TP7 TP8 TP9
m
F 6
m
C19
V V V V V V V V V V V V V V V
0.1 C21 0.1 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 CC 7 4 EE 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 22.1 V V J8 AD845 U4 40 2 3 CW JP17 JP18
V
A TP26 R11 500 BUFFER SJ6
V
F F R14
m m
10k A +DRVDD C24 0.1 +DRVDD C25 0.1 F
m
F 11 12 13 14 15 16 17 18 20 11 12 13 14 15 16 17 18 20
V m
C22 0.1 C20 U5 TPD R10 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 500 0.1 F +5VD +5VD +5VD
m
DECOUPLING U6 U7 C38 C18 0.1 JP24
V
A G1 G2 A7 A6 A5 A4 A3 A2 A1 A0 GND 74HC541N G1 G2 A7 A6 A5 A4 A3 A2 A1 A0 GND 74HC541N R13 10k 6 4 JP23 2 1 1 F 10 19 10 19
m
AC COUPLE OPTION 74HC04 3 2 1 U5 U5 U5 C17 10 16V DIRECT COUPLE OPTION 12 D7 9 D8 8 D9 7 D10 6 D11 5 D12 4 D13 3 D0 8 D1 7 D2 6 D3 5 D4 4 D5 3 D6 2 A B 5 3 CLK 9 Q1 2N2222 JP14 JP13 A A F TP25
V m V
R8 316 C26 0.1 SPARE GATES A R9 A 50 A U8 J1 R40 R41 +5VA F JP15 CLKB JP16 CLK
m V
DECOUPLING C16 R7 0.1 1k VIN 12
V V
TPD TPC CW 10 12 R16 5k R18 5k A U5 U5
V
F A A U8 U8 2 U8 74HC14 13 98
m
+5VA
V
R6 820 F F C23 R17
m
34 6
m
11 0.1 1k C14 C15 U8 U8 13 10 +5VA 0.1 0.1 98 1 U8
V
A U5 R19 50 A CC 7 4 EE V V 65 11 TP2 VINA1 VINB1 TPC TPD CML AD817 U3 3 2 A J9 ADC_CLK
V V
F
m
R37 33 R38 33 D13 JP21 JP22 JP1 C13 10 16V CLKIN A ADC_CLK C36 15pF A C37 15pF
V
A R36 200 F
m V
C42 0.1 R4 A 50 6 SEC 5 4 TP24 +5VD
V
A T1 +5VA R3 15k 25 24 D13 23 D12 22 D11 21 D10 20 D9 19 D8 18 D7 17 D6 16 D5 15 D4 14 D3 13 D2 12 D1 11 D0 7 A F EXTERNAL REFERENCE DRIVE
V
JP8
m
1 2 3 AVSS1 OTR BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7 BIT8 BIT9 CLK JP10 R5 10k A 29 BIT10 BIT11 BIT12 BIT13 BIT14 C11 0.1 PRI J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 DVDD F A
m
26 AVSS2 39 28 29 30 31 32 34 35 36 37 38 JP7 C8 0.1 DRVDD
V
OUT A R35 NC 63 A NC NC 42 50 AVDD1 U1 V F
m
U2 DVSS J10 C10 GND 8 REF43 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 J8 F AVDD2 0.1 IN 28
m
AD9240MQFP DRVSS 1 V 2 4J 6 8 10 12 14 16 18 20 22 24 C9 AIN 0.1 5 F VREF SENSE REFCOM CAPT CAPB CML VINA VINB BIAS F
m m
A C43 C12 0.1 32 31 33 37 36 39 41 42 35 0.1 A F
m
A C2 0.1 CC BIAS V F R +DRVDD F A
m m
C1 10 16V C6 0.1 + 5 SETS OF PADS TO CONNECT GROUNDS F A
m
CC EE C5 10 16V 1 +5VA +5VD V V +DRVDD JP6 B F F F F F SJ5 +
m m m m m
JP3 JP4 JP5 F F C32 0.1 SJ4 A C33 0.1 A C34 0.1 A C35 0.1 A C40 0.1 A
m m
JP11 TP1 C3 C4 F A
m
32 1 SJ3 +5VA 0.1 0.1 B A C7 0.1 L1 L2 SJ2 L3 L4 L5 R1
V
R2
V
A A JP12 F F F F F SJ1 10k
m
10k A
m m m m
32 C28 22 25V C29 22 25V C30 22 25V C31 22 25V C39 22 25V A A A A F JG1-WIRE ETCH CKT SIDE JG1
m
+ + + + + C41 JP2 0.1 TP18 TP19 TP20 TP21 TP27 TP22 TP23 J2 J3 J4 J5 J11 J6 J7 TPC TPD CC EE CML +5A +5D VINA2 VINA1 VINB2 VINB1 +V –V +5_OR _+3 DGND AGND
Figure 55. Evaluation Board Schematic –22– REV. B