Datasheet AD9433 (Analog Devices) - 13
| 制造商 | Analog Devices |
| 描述 | 12-Bit 105/125 MSPS Analog-To-Digital IF Sampling Converter |
| 页数 / 页 | 21 / 13 — AD9433. SNR = 64dB. SNR = 62dB. –10. SFDR = 78dBFS. SFDR = 70dBFS. –20. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 438 Kb |
| 文件语言 | 英语 |
AD9433. SNR = 64dB. SNR = 62dB. –10. SFDR = 78dBFS. SFDR = 70dBFS. –20. –30. –40. BF d. –50. –60. IT L. –70. –80. –90. –100. –110. –120. 7.5. 15.0. 22.5. 30.0. 37.5
该数据表的模型线
文件文字版本
AD9433 0 0 SNR = 64dB SNR = 62dB –10 –10 SFDR = 78dBFS SFDR = 70dBFS –20 –20 –30 –30 ) ) S –40 S –40 BF d –50 BF d –50 ( ( E E –60 –60 UD UD IT L –70 IT L –70 P P –80 –80 AM AM –90 –90 –100 –100 –110 –110 –120 –120
33 36
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
07-
0 6.25 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5
07-
FREQUENCY (MHz)
97 01
FREQUENCY (MHz)
97 01 Figure 28. FFT: fS = 105 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS, Figure 31. FFT: fS = 125 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled SFDR Mode Enabled
0 0 SNR = 61.2dB SNR = 54.6dB –10 SFDR = 67dBFS –10 SFDR = 58dBFS –20 –20 –30 –30 ) ) S –40 S –40 F B BF d –50 d –50 ( ( E –60 –60 UD UDE IT IT L –70 L –70 P P –80 AM –80 AM –90 –90 –100 –100 –110 –110 –120
4
–120
37
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
03 0 7-
0 6.2 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5
7- 97
FREQUENCY (MHz) FREQUENCY (MHz)
97 01 01 Figure 29. FFT: fS = 105 MSPS, fIN = 250.3 MHz, Differential AIN @ −0.5 dBFS, Figure 32. FFT: fS = 125 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled SFDR Mode Enabled
0 –110 SNR = 55.3dB –10 SFDR = 61dBFS –100 –20 –90 –30 ) S –80 ) F S –40 B d –70 BF d –50 D ( ( M –60 –60 R I UDE –50 IT L –70 RDE P O –40 –80 AM RD- HI –30 –90 T –100 –20 –110 –10 –120
5
0
38
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
03
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
0 7- 7-
FREQUENCY (MHz)
97
AIN LEVEL (dBFS)
97 01 01 Figure 30. FFT: fS = 105 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS, Figure 33. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 150.3 MHz SFDR Mode Enabled and 151.3 MHz, Differential AIN, SFDR Mode Enabled Rev. A | Page 12 of 20 Document Outline FEATURES APPLICATIONS GENERAL INTRODUCTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY EQUIVALENT CIRCUITS THEORY OF OPERATION ENCODE INPUT ENCODE VOLTAGE LEVEL DEFINITION ANALOG INPUT SFDR OPTIMIZATION DIGITAL OUTPUTS VOLTAGE REFERENCE TIMING APPLICATIONS INFORMATION LAYOUT INFORMATION REPLACING THE AD9432 WITH THE AD9433 OUTLINE DIMENSIONS ORDERING GUIDE
33 36
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
07-
0 6.25 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5
07-
FREQUENCY (MHz)
97 01
FREQUENCY (MHz)
97 01 Figure 28. FFT: fS = 105 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS, Figure 31. FFT: fS = 125 MSPS, fIN = 150.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled SFDR Mode Enabled
0 0 SNR = 61.2dB SNR = 54.6dB –10 SFDR = 67dBFS –10 SFDR = 58dBFS –20 –20 –30 –30 ) ) S –40 S –40 F B BF d –50 d –50 ( ( E –60 –60 UD UDE IT IT L –70 L –70 P P –80 AM –80 AM –90 –90 –100 –100 –110 –110 –120
4
–120
37
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
03 0 7-
0 6.2 12.5 18.7 25.0 31.2 37.5 43.7 50.0 56.2 62.5
7- 97
FREQUENCY (MHz) FREQUENCY (MHz)
97 01 01 Figure 29. FFT: fS = 105 MSPS, fIN = 250.3 MHz, Differential AIN @ −0.5 dBFS, Figure 32. FFT: fS = 125 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS, SFDR Mode Enabled SFDR Mode Enabled
0 –110 SNR = 55.3dB –10 SFDR = 61dBFS –100 –20 –90 –30 ) S –80 ) F S –40 B d –70 BF d –50 D ( ( M –60 –60 R I UDE –50 IT L –70 RDE P O –40 –80 AM RD- HI –30 –90 T –100 –20 –110 –10 –120
5
0
38
0 7.5 15.0 22.5 30.0 37.5 45.0 52.5
03
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
0 7- 7-
FREQUENCY (MHz)
97
AIN LEVEL (dBFS)
97 01 01 Figure 30. FFT: fS = 105 MSPS, fIN = 350.3 MHz, Differential AIN @ −0.5 dBFS, Figure 33. Third-Order IMD vs. AIN Level, fS = 105 MSPS, fIN = 150.3 MHz SFDR Mode Enabled and 151.3 MHz, Differential AIN, SFDR Mode Enabled Rev. A | Page 12 of 20 Document Outline FEATURES APPLICATIONS GENERAL INTRODUCTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY EQUIVALENT CIRCUITS THEORY OF OPERATION ENCODE INPUT ENCODE VOLTAGE LEVEL DEFINITION ANALOG INPUT SFDR OPTIMIZATION DIGITAL OUTPUTS VOLTAGE REFERENCE TIMING APPLICATIONS INFORMATION LAYOUT INFORMATION REPLACING THE AD9432 WITH THE AD9433 OUTLINE DIMENSIONS ORDERING GUIDE