link to page 17 link to page 17 link to page 17 link to page 17 link to page 17 link to page 27 AD7651 Transfer FunctionsTable 7. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7651 offers two output Digital Output Code (Hex) codings: straight binary and twos complement. The LSB size is AnalogStraightTwos V DescriptionInputBinaryComplement REF/65536, which is about 38.15 µV. The AD7651’s ideal transfer characteristic is shown in Figure a 21 nd Tabl . e 7 FSR –1 LSB 2.499962 V FFFF1 7FFF1 FSR – 2 LSB 2.499923 V FFFE 7FFE Midscale + 1 LSB 1.250038 V 8001 0001 1 LSB = V REF/65536 Midscale 1.25 V 8000 0000 111...111) Midscale – 1 LSB 1.249962 V 7FFF FFFF ry 111...110 –FSR + 1 LSB 38 µV 0001 8001 111...101 –FSR 0 V 00002 80002 ight Binatra (S 1This is also the code for overrange analog input (VIN – VINGND above VREF – VREFGND). 2 ADC CODE This is also the code for underrange analog input (VIN below VINGND). 000...010 000...001 000...0000V1 LSBVREF – 1 LSB0.5 LSBVREF – 1.5 LSBANALOG INPUT 02964-0-003 Figure 21. ADC Ideal Transfer Function ANALOG20 Ω DIGITAL SUPPLYSUPPLY(3.3V OR 5V)(5V)+++10 µ F100nF10 µ F100nF100nF10 µ FAVDDAGNDDGNDDVDDOVDDOGNDSERIALPORTSCLKREFSDOUTC 4REFBUFIN1R100nF µ C/ µ P/DSPREFGNDBUSYAD7651CNVSTD3U12INANALOG INPUTOB/2C(0V TO 2.5V)SER/PARDVDDCCINGNDPDREFPDPDBUFRESETCSRD BYTESWAPCLOCKNOTES1THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.2THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.3OPTIONAL LOW JITTER.4A 10 µ F CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. 02964-0-004 Figure 22. Typical Connection Diagram Rev. 0 | Page 16 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DEFINITIONS OF SPECIFICATIONS TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE SLAVE SERIAL INTERFACE MICROPROCESSOR INTERFACING APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES LAYOUT EVALUATING THE AD7651’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE