Datasheet AD7940 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | 3 mW, 100 kSPS, 14-Bit ADC in 6-Lead SOT-23 |
| 页数 / 页 | 21 / 6 — AD7940. TIMING SPECIFICATIONS. Table 3. Limit at T , T. MIN. MAX. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 395 Kb |
| 文件语言 | 英语 |
AD7940. TIMING SPECIFICATIONS. Table 3. Limit at T , T. MIN. MAX. Parameter. 3 V. 5 V. Unit. Description. 200. IOL. TO OUTPUT. 1.6V. PIN. 50pF. IOH
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AD7940 TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3. Limit at T , T MIN MAX Parameter 3 V 5 V Unit Description
f 1 250 250 kHz min SCLK 2.5 2.5 MHz max t 16 × t 16 × t min CONVERT SCLK SCLK t 50 50 ns min Minimum quiet time required between bus relinquish and start of QUIET next conversion t 10 10 ns min 1 Minimum CS pulse width t 10 10 ns min 2 CS to SCLK setup time t 2 48 35 ns max 3 Delay from CS until SDATA three-state disabled t 2 120 80 ns max Data access time after SCLK falling edge 4 t 0.4 t 0.4 t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 t 0.4 t ns min SCLK high pulse width 6 SCLK SCLK t 10 10 ns min SCLK to data valid hold time 7 t 3 45 35 ns max SCLK falling edge to SDATA high impedance 8 t 4 1 1 µs typ Power up time from full power-down POWER-UP 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 3 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section.
200
µ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
µ
A IOH
03305-0-002 Figure 2. Load Circuit for Digital Output Timing Specification Rev. A | Page 5 of 20 Document Outline Table of Contents Specifications1F Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Circuit Information Converter Operation Analog Input ADC Transfer Function Typical Connection Diagram Digital Inputs Modes of Operation Normal Mode Power-Down Mode Power vs. Throughput Rate Serial Interface Microprocessor Interfacing AD7940 to TMS320C541 AD7940 to ADSP-218x AD7940 to DSP563xx Application Hints Grounding and Layout Evaluating the AD7940 Performance Outline Dimensions Ordering Guide
AD7940 TIMING SPECIFICATIONS
Sample tested at initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. VDD = 2.50 V to 5.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3. Limit at T , T MIN MAX Parameter 3 V 5 V Unit Description
f 1 250 250 kHz min SCLK 2.5 2.5 MHz max t 16 × t 16 × t min CONVERT SCLK SCLK t 50 50 ns min Minimum quiet time required between bus relinquish and start of QUIET next conversion t 10 10 ns min 1 Minimum CS pulse width t 10 10 ns min 2 CS to SCLK setup time t 2 48 35 ns max 3 Delay from CS until SDATA three-state disabled t 2 120 80 ns max Data access time after SCLK falling edge 4 t 0.4 t 0.4 t ns min SCLK low pulse width 5 SCLK SCLK t 0.4 t 0.4 t ns min SCLK high pulse width 6 SCLK SCLK t 10 10 ns min SCLK to data valid hold time 7 t 3 45 35 ns max SCLK falling edge to SDATA high impedance 8 t 4 1 1 µs typ Power up time from full power-down POWER-UP 1 Mark/space ratio for the SCLK input is 40/60 to 60/40. 2 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 3 t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 4 See the Power vs. Throughput Rate section.
200
µ
A IOL TO OUTPUT 1.6V PIN CL 50pF 200
µ
A IOH
03305-0-002 Figure 2. Load Circuit for Digital Output Timing Specification Rev. A | Page 5 of 20 Document Outline Table of Contents Specifications1F Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Terminology Typical Performance Characteristics Circuit Information Converter Operation Analog Input ADC Transfer Function Typical Connection Diagram Digital Inputs Modes of Operation Normal Mode Power-Down Mode Power vs. Throughput Rate Serial Interface Microprocessor Interfacing AD7940 to TMS320C541 AD7940 to ADSP-218x AD7940 to DSP563xx Application Hints Grounding and Layout Evaluating the AD7940 Performance Outline Dimensions Ordering Guide