Datasheet AD7997, AD7998 (Analog Devices) - 18

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AD7997/AD7998 INTERNAL REGISTER STRUCTURE
The AD7997/AD7998 contain 17 internal registers that are used
CONVERSION
to store conversion results, high and low conversion limits, and
RESULT REGISTER
information to configure and control the device (see Figure 25).
ALERT STATUS
Sixteen are data registers and one is an address pointer register.
REGISTER
Each data register has an address that the address pointer register
CONFIGURATION REGISTER
points to when communicating with it. The conversion result register is the only data register that is read only.
CYCLE TIMER REGISTER ADDRESS POINTER REGISTER DATALOW REGISTER CH1
Because it is the register to which the first data byte of every
DATAHIGH
write operation is written automatically, the address pointer
REGISTER CH1
register does not have and does not require an address. The
D HYSTERESIS
address pointer register is an 8-bit register in which the 4 LSBs
A REGISTER CH1 T
are used as pointer bits to store an address that points to one of
ADDRESS DATALOW A
the AD7997/AD7998’s data registers. The 4 MSBs are used as
POINTER REGISTER CH2 REGISTER
command bits when operating in Mode 2 (see the Modes of
DATAHIGH REGISTER CH2
Operation section). The first byte following each write address is to the address pointer register, containing the address of one
HYSTERESIS REGISTER CH2
of the data registers. The 4 LSBs select the data register to which
DATALOW
subsequent data bytes are written. Only the 4 LSBs of this register
REGISTER CH3
are used to select a data register. On power-up, the address
DATAHIGH
pointer register contains all 0s, pointing to the conversion result
REGISTER CH3
register.
HYSTERESIS REGISTER CH3 Table 7. Address Pointer Register DATALOW C4 C3 C2 C1 P3 P2 P1 P0 REGISTER CH4
0 0 0 0 Register Select
DATAHIGH REGISTER CH4 HYSTERESIS Table 8. AD7997/AD7998 Register Addresses REGISTER CH4 P3 P2 P1 P0 Registers SDA
0 0 0 0 Conversion Result Register (Read)
SERIAL BUS INTERFACE SCL
0 0 0 1 Alert Status Register (Read/Write) 03473-0-025 Figure 25. AD7997/AD7998 Register Structure 0 0 1 0 Configuration Register (Read/Write) 0 0 1 1 Cycle Timer Register (Read/Write) 0 1 0 0 DATALOW Reg CH1 (Read/Write) 0 1 0 1 DATAHIGH Reg CH1 (Read/Write) 0 1 1 0 Hysteresis Reg CH1 (Read/Write) 0 1 1 1 DATALOW Reg CH2 (Read/Write) 1 0 0 0 DATA HIGH Reg CH2 (Read/Write) 1 0 0 1 Hysteresis Reg CH2 (Read/Write) 1 0 1 0 DATALOW Reg CH3 (Read/Write) 1 0 1 1 DATAHIGH Reg CH3 (Read/Write) 1 1 0 0 Hysteresis Reg CH3 (Read/Write) 1 1 0 1 DATALOW Reg CH4 (Read/Write) 1 1 1 0 DATAHIGH Reg CH4 (Read/Write) 1 1 1 1 Hysteresis Reg CH4 (Read/Write) Rev. 0 | Page 18 of 32 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS AD7997 SPECIFICATIONS AD7998 SPECIFICATIONS I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE ADDRESS POINTER REGISTER CONFIGURATION REGISTER CONVERSION RESULT REGISTER LIMIT REGISTERS DATAHIGH Register CH1/CH2/CH3/CH4 DATALOW Register CH1/CH2/CH3/CH4 Hysteresis Register (CH1/CH2/CH3/CH4) Using the Limit Registers to Store Min/Max Conversion Result ALERT STATUS REGISTER (CH1 TO CH4) CYCLE TIMER REGISTER SAMPLE DELAY AND BIT TRIAL DELAY SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7997/AD7998 WRITING TO THE ADDRESS POINTER REGISTER FOR A SUBSEQUENT REA WRITING A SINGLE BYTE OF DATA TO THE ALERT STATUS REGISTER O WRITING TWO BYTES OF DATA TO A LIMIT, HYSTERESIS, OR CONFIGU READING DATA FROM THE AD7997/AD7998 ALERT/BUSY PIN SMBus ALERT BUSY PLACING THE AD7997-1/AD7998-1 INTOHIGH SPEED MODE THE ADDRESS SELECT (AS) PIN MODES OF OPERATION MODE 1—USING THE PIN MODE 2 – COMMAND MODE MODE 3—AUTOMATIC CYCLE INTERVAL MODE OUTLINE DIMENSIONS ORDERING GUIDE RELATED PARTS IN I2C-COMPATIBLE ADC PRODUCT FAMILY