Datasheet AD7328 (Analog Devices) - 19

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AD7328 Data Sheet TYPICAL CONNECTION DIAGRAM V+ 5V
Figure 32 shows a typical connection diagram for the AD7328.
AGND
In this configuration, the AGND pin is connected to the analog
VIN+ VDD VCC
ground plane of the system, and the DGND pin is connected to
AD73281
the digital ground plane of the system. The analog inputs on the
V
AD7328 can be configured to operate in single-ended, true dif-
SS
ferential, or pseudo differential mode. The AD7328 can operate with either an internal or external reference. In Figure 32, the AD7328 is configured to operate with the internal 2.5 V reference.
V–
026 A 680 nF decoupling capacitor is required when operating with
1ADDITIONAL PINS OMITTED FOR CLARITY.
4852- 0 the internal reference. Figure 33. Single-Ended Mode Typical Connection Diagram The VCC pin can be connected to either a 3 V or 5 V supply voltage.
True Differential Mode
VDD and VSS are the dual supplies for the high voltage analog The AD7328 can have four true differential analog input pairs. input structures. The voltage on these pins must be equal to or Differential signals have some benefits over single-ended greater than the highest analog input range selected on the analog signals, including better noise immunity based on the device’s input channels (see Table 6 for more information). The VDRIVE pin common-mode rejection and improvements in distortion is connected to the supply voltage of the microprocessor. The performance. Figure 34 defines the configuration of the true voltage applied to the VDRIVE input controls the voltage of the differential analog inputs of the AD7328. serial interface. VDRIVE can be set to 3 V or 5 V.
VIN+ +15V VCC +2.7V TO +5.25V + + 0.1µF 10µF 10µF 0.1µF AD73281 VIN– V 1 V DD CC +3V SUPPLY
027
VDRIVE 10µF + 0.1µF 1ADDITIONAL PINS OMITTED FOR CLARITY.
04852-
AD7328 V
Figure 34. True Differential Inputs
IN0 VIN1 CS VIN2 DOUT
The amplitude of the differential signal is the difference
µC/µP ANALOG INPUTS: VIN3 SCLK ±10V, ±5V, ±2.5V,
between the signals applied to the V
V
IN+ and VIN− pins in
IN4 0V TO +10V DIN VIN5
each differential pair (VIN+ − VIN−). VIN+ and VIN− should
VIN6
be simultaneously driven by two signals of equal amplitude,
VIN7 DGND SERIAL INTERFACE
dependent on the input range selected, that are 180° out of
REFIN/OUT 680nF
phase. Assuming the ±4 × V
V 1 AGND
REF mode, the amplitude of
SS
the differential signal is −20 V to +20 V p-p (2 × 4 × VREF),
–15V +
regardless of the common mode.
0.1µF 10µF 1MINIMUM VDD AND VSS SUPPLY VOLTAGES
25
DEPEND ON THE HIGHEST ANALOG INPUT
0 52- The common mode is the average of the two signals
RANGE SELECTED.
48 0 Figure 32. Typical Connection Diagram (VIN+ + VIN−)/2
ANALOG INPUT
and is therefore the voltage on which the two input signals are
Single-Ended Inputs
centered. The AD7328 has a total of eight analog inputs when operating This voltage is set up externally, and its range varies with reference in single-ended mode. Each analog input can be independently voltage. As the reference voltage increases, the common-mode programmed to one of the four analog input ranges. In applications range decreases. When the differential inputs are driven with an where the signal source is high impedance, it is recommended amplifier, the actual common-mode range is determined by the to buffer the signal before applying it to the ADC analog inputs. amplifier’s output swing. If the differential inputs are not driven Figure 33 shows the configuration of the AD7328 in single- from an amplifier, the common-mode range is determined by ended mode. the supply voltage on the VDD supply pin and the VSS supply pin. When a conversion takes place, the common mode is rejected, resulting in a noise-free signal of amplitude −2 × (4 × VREF) to +2 × (4 × VREF), corresponding to Digital Codes −4096 to +4095. Rev. C | Page 18 of 36 Document Outline Features General Description Functional Block Diagram Product Highlights Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Output Coding Transfer Functions Analog Input Structure Track-and-Hold Section Typical Connection Diagram Analog Input Single-Ended Inputs True Differential Mode Pseudo Differential Inputs Driver Amplifier Choice Registers Addressing Registers Control Register Sequence Register Range Registers Sequencer Operation Reference VDRIVE Temperature Indicator Modes of Operation Normal Mode (PM1 = PM0 = 0) Full Shutdown Mode (PM1 = PM0 = 1) Autoshutdown Mode (PM1 = 1, PM0 = 0) Autostandby Mode (PM1 = 0, PM0 = 1) Power vs. Throughput Rate Serial Interface Microprocessor Interfacing AD7328 to ADSP-21xx AD7328 to ADSP-BF53x Applications Information Layout and Grounding Power Supply Configuration Outline Dimensions Ordering Guide