Datasheet AD7986 (Analog Devices) - 6

制造商Analog Devices
描述18-Bit, 2 MSPS PulSAR 15 mW ADC in QFN
页数 / 页29 / 6 — Data Sheet. AD7986. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. …
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Data Sheet. AD7986. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. Min. Typ. Max. Unit. 500µA. IOL. TO SDO. 1.4V. 20pF. IOH. 10% VIO. 90% VIO. tDELAY

Data Sheet AD7986 TIMING SPECIFICATIONS Table 4 Parameter Symbol Min Typ Max Unit 500µA IOL TO SDO 1.4V 20pF IOH 10% VIO 90% VIO tDELAY

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Data Sheet AD7986 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4. Parameter Symbol Min Typ Max Unit
Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode) tCONV 400/500 ns Acquisition Time tACQ 100 ns Time Between Conversions (Turbo Mode/Normal Mode) tCYC 500/660 ns CNV Pulse Width (CS Mode) tCNVH 10 ns Data Read During Conversion (Turbo Mode/Normal Mode) tDATA 200/300 ns Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge tQUIET 20 ns SCK Period (CS Mode) tSCK 9 ns SCK Period (Chain Mode) tSCK 11 ns SCK Low Time tSCKL 3.5 ns SCK High Time tSCKH 3.5 ns SCK Falling Edge to Data Remains Valid tHSDO 2 ns SCK Falling Edge to Data Valid Delay tDSDO 6 ns CNV or SDI Low to SDO D17 MSB Valid (CS Mode) tEN 10 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 8 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 4 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns SDI High to SDO High (Chain Mode with Busy Indicator) tDSDOSDI 5 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA IOL TO SDO 1.4V CL 20pF
002
500µA IOH
07956- Figure 2. Load Circuit for Digital Interface Timing
10% VIO 90% VIO tDELAY tDELAY V 1 IH V 1 IH 1 V 1 VIL IL 1MINIMUM V
003
IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3.
07956- Figure 3. Voltage Levels for Timing Rev. D | Page 5 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION CONVERSION MODES OF OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Internal Reference, REF = 4.096V (PDREF = Low) External 1.2 V Reference and Internal Buffer (PDREF = High) External Reference (PDREF = High, REFIN = Low) Reference Decoupling POWER SUPPLY DIGITAL INTERFACE DATA READING OPTIONS Reading During Conversion, Fast Hosts (Turbo or Normal Mode) Split-Reading, Any Speed Host (Turbo or Normal Mode) Reading During Acquisition, Any Speed Hosts (Turbo or Normal Mode) /CS MODE, 3-WIRE WITHOUT BUSY INDICATOR /CS MODE, 3-WIRE WITH BUSY INDICATOR /CS MODE, 4-WIRE WITHOUT BUSY INDICATOR /CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATION HINTS LAYOUT EVALUATING THE PERFORMANCE OF THE AD7986 OUTLINE DIMENSIONS ORDERING GUIDE