Datasheet AD9268 (Analog Devices) - 4

AD9268 GENERAL DESCRIPTION
The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS The ADC output data can be routed directly to the two external analog-to-digital converter (ADC). The AD9268 is designed to 16-bit output ports. These outputs can be set to either 1.8 V support communications applications where high performance, CMOS or LVDS. combined with low cost, small size, and versatility, is desired. Flexible power-down options allow significant power savings, The dual ADC core features a multistage, differential pipelined when desired. architecture with integrated output error correction logic. Each Programming for setup and control is accomplished using a 3-wire ADC features wide bandwidth, differential sample-and-hold SPI-compatible serial interface. analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design consid- The AD9268 is available in a 64-lead LFCSP and is specified over erations. A duty cycle stabilizer is provided to compensate for the industrial temperature range of −40°C to +85°C. variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. Rev. A | Page 3 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE