Datasheet AD7985 (Analog Devices) - 6

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Data Sheet AD7985 TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1
Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Conversion Time: CNV Rising Edge tCONV Turbo mode/normal mode 320/420 ns to Data Available Acquisition Time tACQ 80 ns Time Between Conversions tCYC Turbo mode/normal mode 400/500 ns CNV Pulse Width tCNVH CS mode 10 ns Data Read During Conversion tDATA Turbo mode/normal mode 190/290 ns Quiet Time During Acquisition from Last SCK tQUIET 20 ns Falling Edge to CNV Rising Edge SCK Period tSCK CS mode 9 ns tSCK Chain mode 11 ns SCK Low Time tSCKL 3.5 ns SCK High Time tSCKH 3.5 ns SCK Falling Edge to Data Remains Valid tHSDO 2 ns SCK Falling Edge to Data Valid Delay tDSDO 4 ns CNV or SDI Low to SDO D15 MSB Valid tEN 5 ns CNV or SDI High or Last SCK Falling Edge tDIS CS mode 8 ns to SDO High Impedance SDI Valid Setup Time from CNV Rising Edge tSSDICNV 4 ns SDI Valid Hold Time from CNV Rising Edge tHSDICNV CS mode 0 ns tHSDICNV Chain mode 0 ns SCK Valid Setup Time from CNV Rising Edge tSSCKCNV Chain mode 5 ns SCK Valid Hold Time from CNV Rising Edge tHSCKCNV Chain mode 5 ns SDI Valid Setup Time from SCK Falling Edge tSSDISCK Chain mode 2 ns SDI Valid Hold Time from SCK Falling Edge tHSDISCK Chain mode 3 ns SDI High to SDO High tDSDOSDI Chain mode with busy indicator 15 ns 1 See Figure 2 and Figure 3 for load conditions.
500µA IOL TO SDO 1.4V CL 20pF
002
500µA IOH
07947- Figure 2. Load Circuit for Digital Interface Timing
10% VIO 90% VIO tDELAY tDELAY V 1 IH V 1 IH 1 V 1 VIL IL 1MINIMUM V
003
IH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 3.
07947- Figure 3. Voltage Levels for Timing Rev. C | Page 5 of 28 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION CONVERSION MODES OF OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Internal Reference, REF = 4.096 V (PDREF Low) External 1.2 V Reference and Internal Buffer (PDREF High) External Reference (PDREF High, REFIN Low) Reference Decoupling POWER SUPPLY DIGITAL INTERFACE DATA READING OPTIONS Reading During Conversion, Fast Host (Turbo or Normal Mode) Split-Reading, Any Speed Host (Turbo or Normal Mode) Reading During Acquisition, Any Speed Host (Turbo or Normal Mode) /CS MODE, 3-WIRE WITHOUT BUSY INDICATOR /CS MODE, 3-WIRE WITH BUSY INDICATOR /CS MODE, 4-WIRE WITHOUT BUSY INDICATOR /CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATIONS INFORMATION LAYOUT EVALUATING THE AD7985 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE