Datasheet AD9261 (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 10 MHz Bandwidth, 30 MSPS to 160 MSPS Continuous Time Sigma-Delta ADC |
| 页数 / 页 | 29 / 4 — AD9261. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter Temp. Min. … |
| 文件格式/大小 | PDF / 624 Kb |
| 文件语言 | 英语 |
AD9261. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter Temp. Min. Typ. Max. Unit
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AD9261 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.02 ±0.15 % FSR Gain Error Full ±0.7 ±3.0 % FSR Integral Nonlinearity (INL)2 Full ±1.5 LSB TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 V Input Resistance Full 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 V Supply Current I 2 AVDD Full 74 83 mA I 2 CVDD PLL Enabled Full 57 654 mA I 2 CVDD PLL Disabled Full 8.0 8.8 mA I 2 DVDD Full 100 108 mA I 2 DRVDD (1.8 V) Full 5.5 5.8 mA I 2 DRVDD (3.3 V) Full 10 mA POWER CONSUMPTION Sine Wave Input2 PLL Disabled Full 340 370 mW Sine Wave Input2 PLL Enabled Full 425 465 mW Power-Down Power Full 20 mW Standby Power2 Full 7 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. 0 | Page 3 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide
AD9261 SPECIFICATIONS DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS, unless otherwise noted.
Table 1. Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits ANALOG INPUT BANDWIDTH 10 MHz ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±0.02 ±0.15 % FSR Gain Error Full ±0.7 ±3.0 % FSR Integral Nonlinearity (INL)2 Full ±1.5 LSB TEMPERATURE DRIFT Offset Error Full ±1.5 ppm/°C Gain Error Full ±50 ppm/°C INTERNAL VOLTAGE REFERENCE 490 500 510 mV ANALOG INPUT Input Span, VREF = 0.5 V Full 2 V p-p diff Common-Mode Voltage Full 1.7 1.8 1.9 V Input Resistance Full 1 kΩ POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V CVDD Full 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 3.6 V Supply Current I 2 AVDD Full 74 83 mA I 2 CVDD PLL Enabled Full 57 654 mA I 2 CVDD PLL Disabled Full 8.0 8.8 mA I 2 DVDD Full 100 108 mA I 2 DRVDD (1.8 V) Full 5.5 5.8 mA I 2 DRVDD (3.3 V) Full 10 mA POWER CONSUMPTION Sine Wave Input2 PLL Disabled Full 340 370 mW Sine Wave Input2 PLL Enabled Full 425 465 mW Power-Down Power Full 20 mW Standby Power2 Full 7 mW Sleep Power Full 3 4 mW 1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted. 2 Measured with a low input frequency, full-scale sine wave. Rev. 0 | Page 3 of 28 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications DC Specifications AC Specifications Digital Decimation Filtering Characteristics Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Direct Clocking Internal PLL Clock Distribution External PLL Control PLL Autoband Select Jitter Considerations Power Dissipation and Standby Mode Digital Engine Bandwidth Selection Decimation Filters Sample Rate Converter Cascaded Filter Responses Digital Outputs Digital Output Format Overrange (OR) Condition Timing Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Memory Map Memory Map Definitions Outline Dimensions Ordering Guide